Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
608 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
The Receive Pause Quantum register decrement every 512 bit times immediately, following the PFC
frame reception. For test purposes, the retry test bit can be set (bit 12 in the Network Configuration
register) which causes the Receive Pause Quantum register to decrement every RX_CLK cycle once
transmission has stopped.
The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Receive Pause Quantum
register decrements to zero and it is enabled. This interrupt is also set when a zero quantum pause frame
is received.
3.8.2.
PFC Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit priority based pause frame bit
of the Network Control register. If bit 17 of the Network Control register is written with “1”, a PFC pause
frame will be transmitted providing the MAC Transmitter is enabled (bit 3) in the Network Control register.
When bit 17 of the Network Control register is set to “1”, the fields of the priority base pause frame will be
built using the values stored in the Transmit PFC Pause register.
Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between
the current frame and the next frame due to be transmitted.
Transmitted pause frames comprise of the following:
−
A destination address of 0180C2000001
h
−
A source address taken from Specific Address 1 register
−
A Type ID of 8808h (MAC control frame)
−
A pause opcode of 0101h
−
A priority enable vector taken from the Transmit PFC Pause register
−
8 pause quanta in 4 registers (ETHERNETn_tx_pause_quantum,
ETHERNETn_tx_pause_quantum1, ETHERNETn_tx_pause_quantum2,
ETHERNETn_tx_pause_quantum3)
−
Fill of 00h to take the frame to minimum frame length
−
Valid FCS
The pause quantum registers used in the generated frame will depend on the trigger source for the frame
as follows:
−
If bit 17 of the Network Control register is written with “1” then the priority enable vector of the
priority based pause frame will be set equal to the value stored in the Transmit PFC Pause register
bits [7:0]. For each entry equal to “0” in the Transmit PFC Pause register [15:8], the pause quantum
field of the pause frame associated with that entry will be taken from the Transmit Pause Quantum
register. For each entry equal to "1" in the Transmit PFC Pause register [15:8], the pause quantum
associated with that entry will be "0". The Transmit Pause Quantum register resets to a value of
FFFF
h
giving maximum pause quantum as initial value.
−
The pause quantum registers are classed as static and these registers should be updated only
when no PFC frame is transmitted.
−
To use the eight priority pause quanta stored in the four Transmit Pause Quantum registers, set bit
24 to “1” in the Network Control register.
After transmission, a pause frame transmit interrupt will be issued (bit 14 of the Interrupt Status register)
and the only statistics register that will be incremented will be the Pause Frames Transmitted register.
PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods.