Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 329
5.14.2.
Pulse Counter Interrupt Flag Register (ADC12Bn_PCIRQ1)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME PCIRQ63 PCIRQ62 PCIRQ61 PCIRQ60 PCIRQ59 PCIRQ58 PCIRQ57 PCIRQ56
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME PCIRQ55 PCIRQ54 PCIRQ53 PCIRQ52 PCIRQ51 PCIRQ50 PCIRQ49 PCIRQ48
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME PCIRQ47 PCIRQ46 PCIRQ45 PCIRQ44 PCIRQ43 PCIRQ42 PCIRQ41 PCIRQ40
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME PCIRQ39 PCIRQ38 PCIRQ37 PCIRQ36 PCIRQ35 PCIRQ34 PCIRQ33 PCIRQ32
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] PCIRQ63 to 32 : Pulse Counter Interrupt flags
Bit Description
0 Pulse counter interrupt not detected.
1 Pulse counter interrupt detected.
This register returns the status of the pulse counter interrupt flag which is set when positive counter
ADC12B_PCCTRL32 to 63.PCTPCT of the corresponding logical channel decrements to zero. The
positive counter and negative counter are stopped as long as the pulse counter interrupt flag of the
appropriate channel is set.
This bit is cleared by writing "1" to the corresponding bit in the ADC12Bn_PCIRQC1 register.
This bit is identical to the PCIRQ bit in the corresponding ADC12Bn_CHSTAT32 to 63 register.