CHAPTER 21:Ethernet MAC
800
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.127.
MSB Buffer Queue Base Address Register
(ETHERNETn_msb_buff_q_base_addr_reg)
Description of MSB Buffer Queue Base Address register is shown.
REGISTER_NAME
ETHERNETn_msb_buff_q_base_addr_reg
OFFSET
0x4C8
ACCESS_SIZE
W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
msb_buff_q_base_addr[31:24]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
msb_buff_q_base_addr[23:16]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
msb_buff_q_base_addr[15:8]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
BIT_OFFSET
7
6
5
4
3
2
1
0
BIT_NAME
msb_buff_q_base_addr[7:0]
ACCESS_TYPE
R/W
PROT_TYPE
Wp
INITIAL_VALUE
0x00
[bit31:0] msb_buff_q_base_addr: Upper 32-bit Buffer Queue Base Address
Содержание S6J3200 Series
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