Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 345
5.19.2.
A/D Channel Trigger Overrun Flag Register (ADC12Bn_TRGOR1)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TRGOR63 TRGOR62 TRGOR61 TRGOR60 TRGOR59 TRGOR58 TRGOR57 TRGOR56
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME TRGOR55 TRGOR54 TRGOR53 TRGOR52 TRGOR51 TRGOR50 TRGOR49 TRGOR48
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TRGOR47 TRGOR46 TRGOR45 TRGOR44 TRGOR43 TRGOR42 TRGOR41 TRGOR40
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TRGOR39 TRGOR38 TRGOR37 TRGOR36 TRGOR35 TRGOR34 TRGOR33 TRGOR32
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] TRGOR63 to 32 : A/D Channel Trigger Overrun flags
Bit Description
0 No trigger overrun happened
1 Trigger overrun occurred
This bit is set to "1" under following conditions:
−
Conversion request is issued although the corresponding trigger status bits
ADC12Bn_TRGST1.TRGST and ADC12Bn_CHSTAT32 to 63.TRGST are already set to "1"
−
Software and hardware trigger are issued at the same cycle and corresponding trigger type
ADC12Bn_CHCTRL32 to 63.TRGTYP[1:0] is set to "01"
Writing "1" to the corresponding bit in the ADC12Bn_TRGORC1 register clears this bit.