Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 22:Media Local Bus Interface (MediaLB)
868 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Note:
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In IO Mode, the STS[9] bit cannot be programmed to generate a channel interrupt. System
software must poll this bit following a Receive Packet Abort (see MLBn_CSCR:STS[8]). As each
quadlet of the broken packet is popped from the local channel buffer, software must check to see
if the next quadlet is the start of a new packet. When software detects a Receive Packet Start, it
can start processing valid data.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
[bit8] STS : STS[8]
This bit has different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is Previous Buffer Protocol Error bit. When set, this bit indicates that either a transmit
channel has detected an RxStatus of ReceiverProtocolError (0x72), a receive channel has detected an
invalid command for this channel type, or an additional AsyncStart (0x20) or ControlStart (0x30)
command has been received while in the middle of a packet.
The setting of this bit generates a maskable channel interrupt to system software. This bit is valid for all
receive channels and valid for only asynchronous and control transmit channels.
In IO mode this is Receive Packet Abort bit. When set, this bit indicates that a receive channel has
detected an aborted packet. Received packets are aborted if the receiver generates a break response,
ReceiverBreak (0x70), or detects a transmitter packet break command; ControlBreak (0x36) or
AsyncBreak (0x26).
This bit can also indicate the receive channel has detected a transmit command protocol error. The
setting of this bit generates a maskable channel interrupt to system software. This interrupt can be used
by system software to detect when it has encountered the beginning of an aborted packet. This bit is valid
for asynchronous and control receive channels only.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by softwar
[bit7] STS : STS[7] - Reserved
Read value is "0". Always write "0" to this bits.
[bit6] STS : STS[6] - Lost Frame Synchronization bit
When set, this bit indicates that the logical channel has lost synchronization with the MediaLB frame. The
setting of this bit generates a maskable channel interrupt to system software. This bit is valid for
synchronous channels only.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
[bit5] STS : STS[5]
This bit has a different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is Host Bus Error bit. When set, this bit indicates that an HBI bus error has been
detected. The setting of this bit generates a non-maskable channel interrupt to system software.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.