Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 22:Media Local Bus Interface (MediaLB)
850 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.6.
MediaLBn Synchronous Base Address Configuration Register
(MLBn_SBCR)
MediaLBn Synchronous Base Address Configuration Register (MLBn_SBCR) defines the base address
for synchronous receive/transmit system memory buffers.
REGISTER_NAME YOURPERIn_CSRi
OFFSET 0 + i*4
ACCESS_SIZE B H W
MULTIPLE 0:15
NUMERIC_TYPE
OTHER
MediaLB Synchronous Base Address Configuration Register (MLBn_SBCR)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME SRBA[15] SRBA[14] SRBA[13] SRBA[12] SRBA[11] SRBA[10] SRBA[9] SRBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME SRBA[7] SRBA[6] SRBA[5] SRBA[4] SRBA[3] SRBA[2] SRBA[1] SRBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME STBA[15] STBA[14] STBA[13] STBA[12] STBA[11] STBA[10] STBA[9] STBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME STBA[7] STBA[6] STBA[5] STBA[4] STBA[3] STBA[2] STBA[1] STBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:16] SRBA[15:0] : Upper Half of Synchronous Receive Base Address for DMA
mode
These bits allow the system software to define the base address (SRBA[31:16]) for synchronous receive
system memory buffers.
This base address is shared by all synchronous receive channels and defines the upper 16 bits of the
32-bit address for these channels.
This bit field is only used in DMA mode. In IO mode these bits are not used.