Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 23:Stereo Audio DAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 883
This interrupt indicates an error case when the DMA tries to transfer more data to the FIFO buffer than
configured by DACTRL:FEST + 1.
3.7.
AHB Slave Interface
AHB slave interface controls the read/write access to the FIFO and register access. Table 2 shows the
access type of the corresponding AHB.
Table 3 AHB Slave Interface
Item Support
Burst transfer
Stereo Audio DAC supports the burst transfer. However, the burst transfer is
processed as a single transfer.
Protection control not support
response OKAY and ERROR only
Access size 8,16,32bit only
Width of address 10bit
The following accesses cause the slave error response.
1) When the access destination is an address that does not exist in the memory map.
2) The write access was done to the read only register.
3) When the access size is a size not supported. (For example, it accessed DADR with 8bit or 16bit.)
3.8.
FIFO
FIFO for data is built into the Stereo Audio DAC module. Table 3 shows the specifications of the FIFO. It
accesses FIFO through the DADR0-15 register. It becomes possible to access FIFO by accessing either
of register of DADR0-15. The access to FIFO is not related to the address of DADR. The access to FIFO
is done in order of the access regardless of the address of DADR0-15.
Table 4 Outline of FIFO
Item Content
Width of data 32bit
Width of address 5bit
Depth 24
Composition Register