Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
612 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Type ID Match 1 Register (ETHERNETn_spec_type_1)
Type ID Match 2 Register (ETHERNETn_spec_type_2)
Type ID Match 3 Register (ETHERNETn_spec_type_3)
Type ID Match 4 Register (ETHERNETn_spec_type_4)
IPG Stretch Register (ETHERNETn_stretch_ratio)
Stacked VLAN Register (ETHERNETn_stacked_vlan)
Transmit PFC Pause Register (ETHERNETn_tx_pfc_pause)
Specific Address Mask 1 Bottom Register (ETHERNETn_mask_add1_bottom)
Specific Address Mask 1 Top Register (ETHERNETn_mask_add1_top
Receive DMA Data Buffer Address Mask Register (ETHERNETn_dma_addr_or_mask)
RX PTP Unicast IP Destination Address Register (ETHERNETn_rx_ptp_unicast)
TX PTP Unicast IP Destination Address Register (ETHERNETn_tx_ptp_unicast)
IEEE 1588 Timer Comparison Value Nanoseconds Register (ETHERNETn_tsu_nsec_cmp)
IEEE 1588 Timer Comparison Value Seconds Bottom Register (ETHERNETn_tsu_sec_cmp)
IEEE 1588 Timer Comparison Value Seconds Top Register (ETHERNETn_tsu_msb_sec_cmp)
PTP Event Frame Transmitted Seconds [47:32] Register (ETHERNETn_tsu_ptp_tx_msb_sec)
PTP Event Frame Received Seconds [47:32] Register (ETHERNETn_tsu_ptp_rx_msb_sec)
PTP Peer Event Frame Transmitted Seconds [47:32] Register (ETHERNETn_tsu_peer_tx_msb_sec)
PTP Peer Event Frame Received Seconds [47:32] Register (ETHERNETn_tsu_peer_rx_msb_sec)
Identification and Revision Register (ETHERNETn_revision_reg)
Statistics registers. These registers reset to zero on a read and stick at all ones when they count to
their maximum value. They should be read frequently enough to prevent loss of data. The receive
statistics registers are only incremented when receive enable bit (ETHERNETn_network_control[2]) is
set in the Network Control register. The statistics registers optionally have a snapshot capability which,
when exercised, will simultaneously store and clear the current values of all the statistics registers into
a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The
snapshot is controlled using bit 13 of the Network Control register. The read snapshot control indicated
by bit 14 of the Network Control register determines whether the processor reads the snapshot
registers (logic 1) or the incrementing registers (logic 0). The default Ethernet MAC configuration does
not support the snapshot capability. All the statistics registers are read only. For test purposes they may
be written by setting bit 7 (Write Enable) in the Network Control register. Setting bit 6 (increment
statistics) in the Network Control register causes all the statistics registers to increment by one, again
for test purposes. Once a statistics register has been read, it is automatically cleared. The statistics
register block contains the following registers:
Octets Transmitted Bottom Register (ETHERNETn_octets_txed_bottom)
Octets Transmitted Top Register (ETHERNETn_octets_txed_top)
Frames Transmitted Register (ETHERNETn_frames_txed_ok)
Broadcast Frames Transmitted Register (ETHERNETn_broadcast_txed)
Multicast Frames Transmitted Register (ETHERNETn_multicast_txed)
Pause Frames Transmitted Register (ETHERNETn_pause_frames_txed)