Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 947
4.10.
Status Register (I2Sn_STATUS)
This register gives status information.
Status Register (I2Sn_STATUS)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TBERR RBERR FERR TXUDR1 TXUDR0 TXOVR RXUDR RXOVR
ACCESS_TYPE R,WX R,WX R,W1 R,W1 R,W1 R,W1 R,W1 R,W1
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME read0 read0 read0 read0 EOPI BSY TXFI RXFI
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R,W1 R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TXNUM[7] TXNUM[6] TXNUM[5] TXNUM[4] TXNUM[3] TXNUM[2] TXNUM[1] TXNUM[0]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME RXNUM[7] RXNUM[6] RXNUM[5] RXNUM[4] RXNUM[3] RXNUM[2] RXNUM[1] RXNUM[0]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31] TBERR : Tx Block Size Error
When I2Sn_DMAACT:TDMACT is "1" and block transfer through DMA transmission channel is more
than I2Sn_INTCNT:TFTH + 1, this bit is set to 1 and the DMA transmission channel is stopped.
When TBERR is "1" and I2Sn_INTCNT:TBERM is "0", interrupt to CPU occurs.
This bit becomes "0" by software reset.