Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 589
If a “Used” bit is read mid way through transmission of a multi buffer frame this is treated as a transmit
error. Transmission stops,
TX_ER
is asserted and the FCS will be bad.
If transmission stops due to a transmit error or a “Used” bit being read, transmission will restart from the
first buffer descriptor of the frame being transmitted when the transmit start bit in the Network Control
register (ETHERNETn_network_control[9]) is rewritten.
3.1.6.
DMA Bursting
When performing data transfers, the burst length used can be programmed using bits [4:0] of the DMA
Configuration register. Either single accesses (burst length = 1) of incrementing bursts of up to 16 can be
used as appropriate.
When there is sufficient space and enough data to be transferred, the burst of programmed length will be
used. If there is not enough data or space available, for example when at the end of a packet or buffer,
burst lengths of less than the programmed burst length value will be issued. Single accesses will be used
when a 4 Kbyte boundary will be crossed by the burst in order not to violate the AXI specification.
When the Ethernet MAC DMA is configured for packet buffer mode, an option to force the Ethernet MAC
DMA to pad the remaining bursts at the end of a buffer or EOP to the programmed burst length value is
available via bits 26 and 25 of the DMA Configuration register. Bit 26 will control the TX and bit 25 the RX.
For RX, the data to burst is padded with "0"s up to the burst boundary defined by burst length. For TX, the
extra data that is read is ignored by the Ethernet MAC DMA. This feature has been included for
performance reasons when AHB/AXI slaves that are being accessed by the Ethernet MAC perform better
when accessed using fixed length bursts. Note enabling this feature will not break the AHB 1Kbyte or the
AXI 4Kbyte boundary rule.
The Ethernet MAC DMA will not terminate bursts premature if receive/transmit operation is disabled by
writing to Network Control register bit 2/3.
3.1.7.
DMA Packet Buffer
The packet buffer DMA mode allows multiple packets to be buffered in both transmit and receive
directions and allows the Ethernet MAC DMA to withstand variable levels of access latencies on the AXI
fabric. This mode offers the most efficient use of the AXI bandwidth.
As described earlier, the Ethernet MAC DMA can be programmed into a low latency mode known as
partial store and forward. When the Ethernet MAC DMA is programmed in full store and forward mode full
packets are buffered providing the opportunity to:
−
Discard packets that are received with errors before they are partially written out of the Ethernet
MAC DMA thus saving AXI bandwidth and driver processing overhead.
−
Retry collided transmit frames from the buffer, thus saving AXI bus bandwidth.
−
Implement transmit IP/TCP/UDP checksum generation offload.
The following figure illustrates the structure of the Ethernet MAC data paths.