Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
938 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.5.
Channel Control Register 1 (I2Sn_MCR1REG)
The Channel Control Register 1 (I2Sn_MCR1REG) controls enable and disable functions to each
channel of sub frame 0.
Channel Control Register 1 (I2Sn_MCR1REG)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME S0CH[31] S0CH[30] S0CH[29] S0CH[28] S0CH[27] S0CH[26] S0CH[25] S0CH[24]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME S0CH[23] S0CH[22] S0CH[21] S0CH[20] S0CH[19] S0CH[18] S0CH[17] S0CH[16]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME S0CH[15] S0CH[14] S0CH[13] S0CH[12] S0CH[11] S0CH[10] S0CH[9] S0CH[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME S0CH[7] S0CH[6] S0CH[5] S0CH[4] S0CH[3] S0CH[2] S0CH[1] S0CH[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] S0CH : Sub Frame 0 Channel Enable
Each bit enables/disables corresponding channel of sub frame 0 (e.g. S0CH[0] bit controls 0th channel
of sub frame 0, S0CH[31] bit controls 31st channel of sub frame 0).
Bit Description
0
The corresponding channel is disabled
Transmission/reception is not performed to the disabled channel.
1
The corresponding channel is enabled
Transmission/reception is performed to the enabled channel.