Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 939
4.6.
Channel Control Register 2 (I2Sn_MCR2REG)
The Channel Control Register 2 (I2Sn_MCR2REG) controls enable and disable functions to each
channel of sub frame 1.
Channel Control Register 2 (I2Sn_MCR2REG)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME S1CH[31] S1CH[30] S1CH[29] S1CH[28] S1CH[27] S1CH[26] S1CH[25] S1CH[24]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME S1CH[23] S1CH[22] S1CH[21] S1CH[20] S1CH[19] S1CH[18] S1CH[17] S1CH[16]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME S1CH[15] S1CH[14] S1CH[13] S1CH[12] S1CH[11] S1CH[10] S1CH[9] S1CH[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME S1CH[7] S1CH[6] S1CH[5] S1CH[4] S1CH[3] S1CH[2] S1CH[1] S1CH[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] S1CH : Sub Frame 1 Channel Enable
Each bit enables/disables corresponding channel of sub frame 1 (e.g. S1CH[0] bit controls 0th channel
of sub frame 1), S1CH[31] bit controls 31st channel of sub frame 1. When frame is 1 sub frame
construction (I2Sn_CNTREG:SBFN is "0"), this is invalid.
Bit Description
0
The corresponding channel is disabled
Transmission/reception is not performed to the disabled channel.
1
The corresponding channel is enabled
Transmission/reception is performed to the enabled channel.