Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
918 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
−
Each FB0, FB1, FB2, FB3, FH0, FH1, and FW indicate AB0, AB1, AB2, AB3, AH0, AH1, and AW
at writing to transmission FIFO after they are right justified
Reception Word Alignment
Figure 3-4 Reception Word Line Chart
This chart shows word line example of when word length is 8.
The word received from serial bus is always written to reception FIFO after being right justified.
Therefore, read access should be performed from AHB bus to I2Sn_RXFDAT0 to 15 in order to read as
follows:
Word length:
−
8 or less: byte 0
−
9- 16: half word 0
−
17-32: all words
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 30 29 28 27 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 6 2 0 26 5 3 7 9 8 4 1
31 30 29 28 27 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 6 2 0 26 5 3 7 9 8 4 1
LSB First
0 1
MSB First
Write to reception FIFO
MLSB
LSB
LSB
LSB
LSB 0
1
I2Sn_RXFDAT0~15
Serial data Input pin shifting direction
BIT extension and right justification
B0 B1 B2 B3 B4 B5 B6 B7
B7 B0 B1 B2 B6 B5 B4 B3
B7 B0 B1 B2 B6 B5 B4 B3
1 1 1 1 1
I2Sn_CNTREG:BEXT =
’0’
1 1 1 1 1 1
0
I2Sn_CNTREG:BEXT =
’1’
I2Sn_CNTREG:BEXT =
’1’
I2Sn_CNTREG:BEXT =
’0’
1