Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 20:Sound Mixer
538 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit10] OUTBCLR: Output buffer initialization
Bit
Description
Read Write
0 Not under initialization Does not have any effect on operation.
1 Initialization wait
Initialize buffer (This bit automatically cleared to 0
following initialization.)
[bit9] PMIS4BCLR: PMIS4 input buffer initialization
[bit8] PMIS3BCLR: PMIS3 input buffer initialization
[bit7] PMIS2BCLR: PMIS2 input buffer initialization
[bit6] PMIS1BCLR: PMIS1 input buffer initialization
[bit5] PMIS0BCLR: PMIS0 input buffer initialization
PMISnBCLR
(n=0 to 4)
Description
Read Write
0 Not under initialization Does not have any effect on operation.
1 Initialization wait
Initialize buffer (This bit automatically cleared
to 0 following initialization.)
Note:
−
PMISn input buffer initialization must not be executed when DMAENCHn bit of MXDRQCTRL
register is 1.
[bit4] WFG4BCLR: WFG4 input buffer initialization
[bit3] WFG3BCLR: WFG3 input buffer initialization
[bit2] WFG2BCLR: WFG2 input buffer initialization
[bit1] WFG1BCLR: WFG1 input buffer initialization
[bit0] WFG0BCLR: WFG0 input buffer initialization
WFGnBCLR
(n=0 to 4)
Description
Read Write
0 Not under initialization Does not have any effect on operation.
1 Initialization wait
Initialize buffer (This bit automatically cleared to 0
following initialization.)
Note:
−
Every channel of WFG0 to 4 has an input buffer for a word (32bit) in the part of "input control".