CHAPTER 27:HyperBus Interface
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
1007
1.
Overview
The HYPERBUSI module provides function and operation for interfacing to the HyperBus memory
devices. The HyperBus achieves both high speed read/write throughput by double data rate interface and
low pin counts. The HYPERBUSI module's features are described in this section.
Features of the HyperBus Interface
Supports operational frequency up to 166MHz
Achieves maximum 333MB/s data throughput by 8 bits bus and few timing signals only
Supports the double data rate interface
Supports two slave devices
Supports XiP operation by dynamic wrapped burst request
2.
Block Diagram
This section shows a block diagram of HYPERBUSI module.
Figure 2-1 Block Diagram of HYPERBUSI
HYPERBUSI Core Logic
AXI
Slave
C
/A
C
o
d
e
r
CS
REG
HYPERBUSI
Wrapper
AXI
Slave
H
y
p
e
rB
u
s
C
o
re
RX
FIFO
R DAT
FIFO
W DAT
FIFO
ADR
FIFO
IENOn
RSTOn
RESETn
WPn
INTn
GPO[1:0]
T
x
/R
x
C
o
n
tr
o
ll
e
r
C
o
n
ti
n
u
o
u
s
R
e
a
d
C
tr
l
DQ[7:0]
8
2
2
1
RWDS
CK, CKn
CSn[1:0]
AXI
2
CK2, CK2n
Содержание S6J3200 Series
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