Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
606 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
The start of an IEEE Std 802.3 pause frame looks like this:
Destination
Address
Source
Address
Type
(MAC Control Frame)
Pause
Opcode
Pause Time
0180C2000001
h
6 bytes 8808
h
0001
h
2 bytes
3.7.1.
IEEE Std 802.3 Pause Frame Reception
Bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set
transmission will pause if a non zero pause quantum frame is received.
If a valid pause frame is received then the Receive Pause Quantum register is updated with the new
frame’s pause time regardless of whether a previous pause frame is active or not. An interrupt (either bit
12 or 13 of the Interrupt Status register) is triggered when a pause frame is received, but only if the
interrupt has been enabled. Pause frames received with non-zero quanta are indicated through the
interrupt bit 12 of the Interrupt Status register. Pause frames received with zero quanta are indicated on
bit 13 of the Interrupt Status register.
Once the Receive Pause Quantum register (ETHERNETn_pause_time) is loaded and the frame currently
being transmitted has been sent, no new frames are transmitted until the pause time reaches zero. The
loading of a new pause time, and hence pausing of transmission, occurs since the Ethernet MAC is
operating in full duplex mode. A valid pause frame is defined as having a destination address that
matches either the address stored in Specific Address 1 register or if it matches the reserved address of
0180C2000001
h
. It must also have the MAC control frame Type ID of 8808
h
and have the pause opcode
of 0001
h
.
Pause frames that have FCS or other errors will be treated as invalid and will be discarded. IEEE Std
802.3 pause frames that are received after Priority based Flow Control (PFC) has been negotiated will
also be discarded. Valid pause frames received will increment the Pause Frames Received statistics
register.
The Receive Pause Quantum register decrements every 512 bit times once transmission has stopped.
For test purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes
the Receive Pause Quantum register to decrement every TX_CLK cycle once transmission has stopped.
The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Receive Pause Quantum
register decrements to zero and it is enabled. This interrupt is also set when a zero quantum pause frame
is received.
3.7.2.
IEEE Std 802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the
Network Control register. If either bit 11 or bit 12 of the Network Control register is written with “1”, an
IEEE Std 802.3 pause frame will be transmitted providing the MAC Transmitter is enabled (bit 3) in the
Network Control register.
Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between
the current frame and the next frame due to be transmitted.
Transmitted pause frames comprise of the following:
−
A destination address of 0180C2000001
h
−
A source address taken from Specific Address 1 register
−
A Type ID of 8808
h
(MAC control frame)