CHAPTER 5:Clock Configuration
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
57
Source Clock
System
Clock Name
Function
Local clock
name
Description
Main clock
Main clock
Indicator PWM
Main clock
-
Main clock
Main clock
LCD Controller
Main clock
-
PLL0 or SSCG0
CLK_LCP1A
12/10/8-BIT Analog to Digital
Converter
No Define
-
PLL0 or SSCG0
CLK_LCP1A
LCD Controller
No Define
-
PLL0 or SSCG0
CLK_LCP1A
Trigger Configuration of Stepper
Motor Controller
No Define
-
PLL0 or SSCG0
CLK_LCP0A
Sound Generator
BCLK
-
PLL0 or SSCG0
CLK_LCP1A
Stepper Motor Controller
CLKP
-
PLL1
CLK_CD2A0
Graphics Subsystem
No Define
Display clock
PLL1
CLK_CD2A0
FPD-LINK Converter
dsp0_clock_o
ut
-
PLL1
CLK_CD2A0
FPD-LINK Converter
dsp1_clock_o
ut
-
PLL2
CLK_CD4
Inter IC Sound (I2S0/I2S1)
ECLK
-
PLL2
CLK_CD4
PCMPWM
PWM_CLK
-
PLL2
CLK_CD4
Stereo Audio DAC
CLKDACI
-
PLL3
CLK_CD5B0
Inter IC Sound (I2S0)
internal clock
-
PLL3
CLK_CD5B0
PCMPWM
No Define
-
PLL3
CLK_CD5
Sound Mixer
No Define
Waveform Generator and Sound Mixer
bus interface clock
PLL3
CLK_CD5A0
Sound Mixer
No Define
Waveform Generator and Sound Mixer
operation clock
PLL3
CLK_CD5
Sound Waveform Generator
No Define
Waveform Generator and Sound Mixer
bus interface clock
PLL3
CLK_CD5A0
Sound Waveform Generator
No Define
Waveform Generator and Sound Mixer
operation clock
PLL3
CLK_CD5B0
Stereo Audio DAC
CLKPI
-
PLL0 or SSCG0
CLK_HAPP1B0
Ethernet MAC
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Inter IC Sound (I2S1)
Internal clock
-
PLL0 or SSCG0
CLK_HAPP1B0
Hyperbus Interface (MCU)
No Define
Operation Clock for Control register
PLL0 or SSCG0
CLK_HPM
Hyperbus Interface (MCU)
No Define
Operation Clock for Main controller
PLL0 or SSCG0
CLK_SYSC0P
Indicator PWM
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Media Local Bus Interface (MediaLB) No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Memory Protection Unit for AHB
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Memory Protection Unit for AHB
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Memory Protection Unit for AXI
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Memory Protection Unit for AXI
No Define
-
PLL0 or SSCG0
CLK_HAPP1B0
Programmable CRC
No Define
-
PLL0 or SSCG0
CLK_LCP0
FPD-LINK Converter
iPCLK
-
SSCG1
CLK_HSSPI
Graphics Subsystem
iHCLK
-
SSCG2
CLK_CD3A0
Graphics Subsystem
No Define
Graphics Core
SSCG2
CLK_CD3A0
Hyperbus Interface (GDC)
No Define
Operation Clock for Control register
SSCG2
CLK_CD3A0
Hyperbus Interface (GDC)
No Define
Operation Clock for Main controller
Содержание S6J3200 Series
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