Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
584 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit s Function
12:0
These bits represent the length of the received frame which may or may not include FCS
depending on whether FCS discard mode is enabled (ETHERNETn_network_configuration[17]
= 1).
With FCS discard mode disabled:
Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12
bits are concatenated with bit 13 of the descriptor.
With FCS discard mode enabled:
Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled, these
12 bits are concatenated with bit 13 of the descriptor.
When Descriptor Timestamp Capture mode is enabled, the following table identifies the added descriptor
words.
Bit Function
Word 2
31:30 Timestamp seconds [1:0] (see Note1)
29:0 Timestamp nanoseconds [29:0] (see Note1)
Word 3
31:4 Unused
3:0 Timestamp seconds [5:2] (see Note1)
Note 1: The timestamp mode is controlled using the RX BD Control register
(ETHERNETn_rx_bd_control).
To receive frames, the receive buffer descriptors must be initialized by writing an appropriate address to
bits [31:2] (or [31:3] for timestamp capture mode) in the first word of each list entry. Bit 0 must be written
with "0". Bit 1 is the wrap bit and indicates the last entry in the buffer descriptor list.
The start location of the receive buffer descriptor list must be written with the receive buffer queue base
address before reception is enabled (ETHERNETn_network_control[2] = 1). Once reception is enabled,
any writes to the RX Buffer Queue Base Address register are ignored. When read, it will return the current
pointer position in the descriptor list, though this is only valid and stable when receive is disabled.
If the filter block indicates that a frame should be copied to memory, the receive data DMA operation
starts writing data into the receive buffer. If an error occurs, the buffer is recovered.
A counter in the Ethernet MAC represents the receive buffer queue pointer and it is not visible through its
register interface. The receive buffer queue pointer increments by two words after each buffer has been
used. It re-initializes to the receive buffer queue base address if any descriptor has its wrap bit set.
As receive buffers are used, the receive buffer manager sets bit 0 of the first word of the descriptor to "1"
indication the buffer has been used.
Software should search through the "Used" bits in the buffer descriptors to find out how many frames
have been received, checking the Start of Frame and End of Frame bits.
When the Ethernet MAC DMA is configured in the partial store and forward mode, received frames are
written out to the sytem memory as soon as enough frame data exists in the RX Packet Buffer Memory.
This may mean several full buffers are used before some error conditions can be detected. If a receive
error is detected the receive buffer currently being written will be recovered. Previous buffers will not be
recovered. As an example, when receiving frames with CRC errors or excessive length, it is possible that