Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 591
If any errors occur on the AXI whilst reading the transmit frame then the fetching of packet data from
memory is halted. The MAC Transmitter will continue to fetch packet data, thereby emptying the TX
Packet Buffer Memory and allowing any good non-erroneous frames to be transmitted successfully.
Once these have been fully transmitted, the status/statistics for the erroneous frame will be updated
and software will be informed via an interrupt that an AXI error occurred. This way, the error is reported
in the correct packet order.
The TX Packet Buffer will only attempt to read more frame data from the system memory when space
is available in the TX Packet Buffer Memory. If space is not available it must wait until a packet fetched
by the MAC Transmitter completes transmission and is subsequently removed from the TX Packet
Buffer Memory. Note that if full store and forward mode is active and if a single frame is fetched that is
too large for the TX Packet Buffer Memory, the frame is flushed and the TX DMA halted with an error
status. This is because a complete frame must be written into the TX Packet Buffer Memory before
transmission can begin.
In full store and forward mode, once the complete transmit frame is written into the TX Packet Buffer
Memory, a trigger is sent across to the MAC Transmitter, which will then begin reading the frame from
the TX Packet Buffer Memory. Since the whole frame is present and stable in the TX Packet Buffer
Memory an underflow of the MAC Transmitter is not possible. The frame is kept in the TX Packet Buffer
Memory until notification is received from the MAC Transmitter that the frame data has either been
successfully transmitted or can no longer be re-transmitted. When this notification is received the frame
is flushed from TX Packet Buffer Memory to make room for a new frame to be fetched from system
memory.
In partial store and forward mode, a trigger is sent across to the MAC Transmitter as soon as sufficient
packet data is available in the TX Packet Buffer Memory, which will then begin fetching the data from it.
If, after this point, the MAC Transmitter is able to fetch data from the TX Packet Buffer Memory faster
than the TX DMA can fill it, an underflow of the MAC Transmitter is possible. In this case, the
transmission is terminated early, and the TX Packet Buffer Memory is flushed. Transmission can only
be restarted by writing to the transmit start bit in the Network Control register
(ETHERNETn_network_control[9]).
In full duplex mode, the frame is removed from the packet buffer on the fly.
 Receive Packet Buffer
The Receive Packet Buffer (RX Packet Buffer) stores frames from the MAC Receiver along with their
status and statistics. Frames with errors are flushed from the RX Packet Buffer Memory, whilst good
frames are pushed onto the AXI Master Interface.
When programmed in full store and forward mode, if the frame has an error the frame data is
immediately flushed from the RX Packet Buffer Memory allowing subsequent frames to utilize the freed
up space. The status and statistics for bad frames are still used to update the Ethernet MAC registers.
To accommodate the status and statistics associated with each frame, up to 2 words (one being for
descriptor timestamp capture when enabled) per packet are reserved at the end of the packet data. If
the packet was bad and requires to be dropped, the status and statistics are the only information held
on that packet.
The RX Packet Buffer will also detect a full condition such that an overflow condition can be detected. If
this occurs subsequent packets will be dropped and an RX overflow interrupt is raised.
For full store and forward, the RX DMA will only begin packet fetches once the status and statistics for a
frame are available. If the frame has a bad status due to a frame error, the status and statistics are