Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 27:HyperBus Interface
1022 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.3.
Interrupt Status Register (HYPERBUSIn_ISR)
HYPERBUSI_ISR indicates the interrupt request source.
REGISTER_NAME HYPERBUSIn_ISR
OFFSET 0x08
ACCESS_SIZE B H W
MULTIPLE
NUMERIC_TYPE
OTHER
Table 4-3 HYPERBUSI Interrupt Status Register Description
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME RFU RFU RFU RFU RFU RFU RFU RPCINTS
ACCESS_TYPE R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R0,WX R,WX
PROT_TYPE
-
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:1] RFU : Reserved for Future Use
When writing this register, this bit should be set to 0 for future compatibility. When reading this register,
this bit is 0 for future compatibility.
[bit0] RPCINTS : HyperBus memory Interrupt Status
This bit indicates the interrupt from HyperBus memory by INTn signal.
While the INT# signal of the HyperBus memory is asserted, this bit is also asserted. In order to clear
this bit, the interrupt of HyperBus memory must be cleared.