Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 25:Programmable CRC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 973
4.5.
CRC Write Register (CRCn_WR)
The input data for the CRC checksum calculation must be written to the CRC Write Register
(CRCn_WR).
CRC Write Register (CRCn_WR)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME CRCWR[31] CRCWR[30] CRCWR[29] CRCWR[28] CRCWR[27] CRCWR[26] CRCWR[25] CRCWR[24]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME CRCWR[23] CRCWR[22] CRCWR[21] CRCWR[20] CRCWR[19] CRCWR[18] CRCWR[17] CRCWR[16]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME CRCWR[15] CRCWR[14] CRCWR[13] CRCWR[12] CRCWR[11] CRCWR[10] CRCWR[9] CRCWR[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME CRCWR[7] CRCWR[6] CRCWR[5] CRCWR[4] CRCWR[3] CRCWR[2] CRCWR[1] CRCWR[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Rp/Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] CRCWR[31:0] : CRC Write Register
The CRCn_WR register contains the input data, for which the CRC checksum is to be calculated.
Writing to this register starts the CRC calculation process. After pre-processing (bit/byte
reflection/swapping) the contents of the CRCn_WR register are passed to the CRC engine (the
contents of CRCn_SEED register are also provided). There it is divided by the content of CRCn_POLY
register in modulo-2 arithmetic to get the final checksum after post-processing (bit/byte
reflection/swapping and XOR'ing).
Note:
−
The size of input data is configured by CRCn_CFG:SZ, where 8, 16, 24, and 32 bits are only
supported as data size. If the input data size is less than 32-bit (i.e. 8, 16, or 24 bits), then the
invalid/unused bits are considered as don’t care (X).