Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 37:Major Changes
1340 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
SSCG
Restriction
57
Note:
−
The frequency of PLLout (output of
PLL/SSCG PLL multiplier circuit) should
be 800MHz or less.
56
Note:
−
The frequency of PLLout (output of
PLL/SSCG PLL multiplier circuit) should
be 800MHz or less.
−
The frequency of
CLK_CPU should be 232MHz or less if its
source clock is SSCG.
#361
Clock Quit 57
Notes:
- ,,,
57
Notes:
- ,,,
- Read/Write access from CPU or DMA
may bring about dead-lock when the clock
source is not supplied to the accessed
clock domain because "handshake" for
AXI transaction cannot be done. If you
want to quit a clock generation for some
clock domain, you also need to configure
an access protection for the domain using
MPU.
#434
DMA Flag
Clear
88 - 88-90 (The row of Remark is added.) #407
DMA channel
activation
factors
88,89
N: Base Timer ch.m - 1
N+1: Base Timer ch.m+1 - 0
88,89
N: Base Timer ch.m+1 - 0
N+1: Base Timer ch.m - 1
#371
Link
information
for headline
3.2.3
215
Notes: − The description of 3.2.2 is also
described in 0 and 3.2.4.
213
Notes:
−
The description of 3.2.2 is also
described in 3.2.3 and 3.2.4.
#368
Kyecode
register
228 - 227 ("3.8 Key Code Register" is added) #359
Note on Port
Output
230 - 229
Notes:
−
Glitch at output port may sometime be
observed when the following case.
1. from input to output
2. from output to input
3. from input to input
4. from output to output
#414
LVD
description
249 - 250
(Clarify the definition of LVDL0/1/2 and
LVDH0/1/2)
#399
Block
Diagram of
Ethernet MAC
580 (APB Slave Interface) 580 (AHB Slave Interface) #365
TYPO in bit
name of
ETHERNET
register
639
(bit29:tsu_timer_comparison interrup)
(bit27:receive_lpi_idication_status_bit_ch
ange)
639
(bit29:tsu_timer_comparison_interrup)
(bit27:receive_lpi_indication_status_bit_c
hange)
#420