Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 23:Stereo Audio DAC
882 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.4.
Switching Clock Frequencies of the Analog DAC
The sequence for changing the clock frequency of the analog DAC is as follows.
1) Write a "1" into the INIT bit of the DACR register. This will cause the data output pins of the digital
interface to output a "00000000h" to the analog DAC.
2) Wait for at least 300 sampling cycles (1/fs) before proceeding to the next step (step 3)
3) Configure the DACCLK and OSR bits of the DAOSR register. The value of the INIT bit must be "1"
throughout this procedure.
4) Wait for at least 300 sampling cycles (1/fs) before proceeding to the next step (step 5)
5) Write a "0" into the INIT bit of the DACR register. This will enable the output data pins of the digital
interface thus providing data to the analog DAC.
3.5.
Minimum Writing Interval between the DAOSR and DACR Registers
The write access to the DAOSR/DACR register mounts the asynchronous circuit from CLKPI to CLKDA.
DABUSY field indicates that the write access to DAOSR/DACR register has not been completed. The
write access to the DAOSR/DACR register is effective only at DABUSY=0. Write access to
DAOSR/DACR register is discarded in the case of DABUSY=1.
This rule applies to the following cases:
−
Write into the DOSR register → Write into the DAOSR register
−
Write into the DOSR register → Write into the DACR register
−
Write into the DCR register → Write into the DOSR register
−
Write into the DCR register → Write into the DCR register
3.6.
Interrupt
The Stereo Audio DAC module interrupts are controlled by three registers: the Interrupt Enable Register
(INTREN), the Interrupt Status Register (INTRSTAT) and the Interrupt Clear Register (INTRCLR). After
reset all interrupts are disabled. If an interrupt is to be used, it must be first enabled. The current status of
an interrupt may be checked at any time in the Interrupt Status Register. The Interrupt Status Register
contents are independent of the enable status of the interrupts. I.e. the Interrupt Status Bits are not
masked by the Interrupt Enable Register.
If an interrupt has occurred, it can be reset by the Interrupt Clear Register. Writing a logic 1 to a bit in the
Interrupt Clear Register clears the corresponding interrupt line as well as the interrupt status bit.
1. Data Request Interrupt
This interrupt indicates there is at least space for another FEST + 1 data samples in the FIFO buffer. I.e.
the Stereo Audio DAC module asserts the interrupt request when a read from the FIFO buffer frees up
another samples slot, so that there are FEST + 1free entries in total.
2. FIFO Buffer Overflow Error Interrupt
This interrupt indicates the CPU has tried to write another data sample to the FIFO buffer when it was
already completely filled.
3. FIFO Buffer Under-Run Error Interrupt
This interrupt indicates an under-run of the FIFO buffer for data samples. I.e. the analog DAC has tried
to read a data sample from the FIFO buffer when it was empty.
4. DMA Block Error Interrupt