Cypress S6J3200 Series, Руководство пользователя

Страница: 1143 / 1355

CHAPTER 31:Memory Protection Unit for AXI
1142 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
transaction highest address matches with multiple regions the permissions corresponding to highest
priority (among all matching region) region is applied.
It is possible that lowest address and highest address may match with different highest priority regions. In
this case the more restrictive permission is applied. Table 6.3-1 shows access permissions with
corresponding restriction index for privileged mode access. Restriction index 1 has the most restrictive
access and access permissions with restriction index 3 has the least restrictive access. This table is
applied when privileged mode attribute of current transaction is of type privileged mode.
Similarly, Table 3-1 shows access permissions with corresponding restriction index for non- privileged
mode access. This table is applied when privileged mode attribute of current transaction is of type
non-privileged mode.
Table 3-2 Restrictive Access Permission Matrix for Privileged Mode Access
AP Bits Access in Privileged Mode Restriction Index
"000", "100" No access 1
"101", "110" read only 2
"001", "010", "011", "111" read, write 3
Table 3-3 Restrictive Access Permission Matrix for Non-privileged Mode Access
AP Bits Access in Non-privileged Mode Restriction Index
"000", "001", "100", "101" No access 1
"010", "110" read only 2
"011", "111" read, write 3

Bus Monitor and Protection Logic
All transactions on the AXI master interfaces are monitored and checked for permitted access.
−
Bus monitor and protection logic within MPU AXI compares the lowest address and highest address
of current transaction with start addresses and end addresses of each region to find region match
where the current transaction matches to among the eight defined regions
−
As explained in Section MPU priority decision the AXI transaction address may match with multiple
regions. The permission attributes of highest priority region are checked against the attributes of
currently applied transaction from AXI master
−
If the attributes of currently applied transaction are within permitted attributes, current transaction is
passed on to the AXI memory interfaces
−
If the attributes are not within permitted attributes current transaction is blocked. The Non Maskable
Interrupt (MPUXn_CTRL0:NMI) flag is set. If the memory protection violation is detected on write
address channel, the address and control information is stored in MPUXn_WERRA and
MPUXn_WERRC registers respectively. If the memory protection violation is detected on read
address channel, the address and control information is stored in MPUXn_RERRA and
MPUXn_RERRC registers respectively. It is possible that memory protection violation is detected
simultaneously on both the channels
−
All further transaction are blocked until the MPUXn_CTRL0:NMI flag is cleared by software. Further
monitoring of AXI master interfaces is also stalled until the MPUXn_CTRL0:NMI flag is cleared
When a transfer is blocked, MPU AXI does the following actions: