Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 20:Sound Mixer
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 513
4.3.
Mixer Date Request Control Register (MXDRQCTRL)
REGISTER_NAME Mixer Date Request Control Register (MXDRQCTRL)
OFFSET 0x008
ACCESS_SIZE B H W
MULTIPLE 31:0
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved Reserved Reserved
DMAEN
CH4
DMAEN
CH3
DMAEN
CH2
DMAEN
CH1
DMAEN
CH0
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R/W R/W R/W R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved Reserved Reserved Reserved FESTCH4[3:0]
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R/W R/W R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME FESTCH3[3:0] FESTCH2[3:0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME FESTCH1[3:0] FESTCH0[3:0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:29] Reserved
This bit is reserved.
Always write "0" to this bit. The read value is "0".
[bit28] DMAENCH4: DMA transfer to PMIS4 request setting
[bit27] DMAENCH3: DMA transfer to PMIS3 request setting
[bit26] DMAENCH2: DMA transfer to PMIS2 request setting