Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 353
5.23.
A/D Converter Comparison Time Setting Register (ADC12Bn_CT)
ADC12Bn_CT register specifies the comparison time of the A/D converter. It is not allowed to update the
value of this register during A/D conversion operation (ADC12Bn_TRGST0 to 1.TRGST and
ADC12Bn_CHSTAT0 to 63.TRGST="1").
REGISTER_NAME ADC12Bn_CT
OFFSET 0x0390
ACCESS_SIZE B H W
MULTIPLE 1
NUMERIC_TYPE
-
OTHER
-
A/D Converter Comparison Time Setting Register (ADC12Bn_CT)
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME CT[15] CT[14] CT[13] CT[12] CT[11] CT[10] CT[9] CT[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME CT[7] CT[6] CT[5] CT[4] CT[3] CT[2] CT[1] CT[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 1 0 0
[bit15:0] CT[15:0] : A/D Converter Comparison Time Setting bits
These bits specify the comparison phase time.
If [CT value < 4]: Comparison time = (CT value x 12 + 4) x Peripheral clock period
If [CT value >= 4]: Comparison time = (CT value x 13) x Peripheral clock period
Do not set CT value to 0.
For specific values of minimum and maximum comparison time, please refer to the Device Data Sheet.