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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 605
BD Control registers) and a bit within Buffer Descriptor Word 0/1 is used to indicate that the timestamp is
present.
3.6.5.
Controlling the Timestamp Unit
The timer is implemented as a 94-bit register with the upper 48 bits counting seconds, the next 30 bits
counting nanoseconds and the lowest 16 bits counting sub-nanoseconds. The lower 46 bits roll over
when they have counted to one second. An interrupt is generated when the seconds increment. The timer
value can be read, written and adjusted through the APB Slave Interface. The timer is clocked with clock
CLK_HAPP1B0 .
There are two modes of operation to control the way the timer varies over time. These are:
Increment timer by a fixed value every clock ( CLK_HAPP1B0 ). This is increment mode.
Increment timer by a fixed value for a fixed number of clocks, followed by an alternative increment value
for a single clock. This is alternative increment mode.
 Increment Mode
The amount by which the timer increments each clock cycle is controlled by the IEEE 1588 Timer
Increment register. Bits [7:0] are the default increment value in nanoseconds and additional 16-bits of
sub-nanoseconds resolution are available using the IEEE 1588 Timer Increment Sub Nanoseconds
register. If the rest of the IEEE 1588 Timer Increment register is written with “0” the timer increments by
the value in bits [7:0], plus the value in IEEE 1588 Timer Nanoseconds register, each clock cycle.
The IEEE 1588 Timer Nanoseconds register allows a resolution of approximately 15 femtoseconds
(1ns/65536).
 Alternative Increment Mode
Bits [15:8] of the IEEE 1588 Timer Increment register are the alternative increment value in
nanoseconds and bits [23:16] are the number of increments after which the alternative increment value
is used. If bits [23:16] are 00
h
then the alternative increment value will never be used.
The timer count value can be compared to a programmable comparison value. For the comparison the 48
bits of the seconds value and the upper 22 bits of the nanoseconds value are used. An interrupt can be
issued when the timer count value and the comparison value in the IEEE 1588 Timer Comparison Value
registers (ETHERNETn_tsu_msb_sec_cmp, ETHERNETn_tsu_sec_cmp, ETHERNETn_tsu_nsec_cmp)
is equal. The interrupt can be enabled with bit 29 in the Interrupt Enable register.
IEEE Std 802.1AS is mostly a subset of IEEE Std 1588. There is one difference in that IEEE Std 802.1AS
uses the Ethernet multicast address 0180C200000E
h
for Sync frame recognition whereas IEEE Std 1588
does not. Ethernet MAC is designed to recognize Sync frames with both IEEE Std 1588 and IEEE Std
802.1AS addresses and so can support their frame recognition simultaneously.
3.7.
MAC IEEE Std 802.3 Pause Frame Support
The Ethernet MAC supports both hardware controlled pause of the transmitter upon reception of a pause
frame and hardware generated pause frame transmission.
Note: See Clause 31, and Annex 31A and 31B of the IEEE Std 802.3 for a full description of pause
operation.