Cypress S6J3200 Series, Руководство пользователя

Страница: 362 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 361
5.29.
A/D Converter Global Status Register (ADC12Bn_STAT)
The register ADC12B_STAT is responsible for storing global status information of A/D Converter, such as
currently converted channel and activity indication bit.
REGISTER_NAME ADC12Bn_STAT
OFFSET 0x03A2
ACCESS_SIZE B H W
MULTIPLE 1
NUMERIC_TYPE
-
OTHER
-
A/D Converter Global Status Register (ADC12Bn_STAT)
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE RX,WX
PROT_TYPE
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved BUSY ACH[5] ACH[4] ACH[3] ACH[2] ACH[1] ACH[0]
ACCESS_TYPE RX,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit15:7] Reserved : Reserved bits
Reading this bit returns an undefined.
Writing data to these bits has no effect on the operation.
[bit6] BUSY : A/D Converter Busy flag
Bit Description
0 A/D Converter is not active, i. e. no A/D conversion is ongoing.
1 A/D Converter is active, i. e. A/D conversion is ongoing.
−
Power-down disable mode (ADC12Bn_CTRL.PDDMD = "1"):
This bit set to "1" when first conversion request (trigger status set to "1") occurs (without A/D
converter resumption time).
This bit clear to "0" when the all trigger status are cleared.
−
Power-down enable mode (ADC12Bn_CTRL.PDDMD = "0"):
This bit is set to "1" when first conversion request (trigger status set to "1") occurs and A/D
Converter resumption time (power-up wait time configured as A/D converter resumption time
register (ADC12Bn_RT)) elapses.
This bit clear to "0" when the all trigger status are cleared.