Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
908 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2.
Configuration and Block Diagram
This section describes the block diagram of I2S.
Figure 2-1 Block Diagram of I2S

Four wire interface is used for full duplex data transfer (separate line for serial data input and serial data
output)

Frame and clock lines are bi-directional. These lines are output when module is configured in master
mode and act as input line in slave mode

DMA controller is used for DMA access
Clocking of I2S

The supply clock of I2S can be internal or external (ECLK) source. This clock is then pre-scaled to
required frequency through I2S control register bits I2Sn_CNTREG:CKRT[5:0]

Frame frequency can be adjusted using I2Sn_CNTREG:OVHD[9:0] bits
SDI
SDO
R W
FIFO SWITCH
Registers
Clock / Frame
Sync. Gen.
Shift Register Control
Bit
−alignment Control
R W
FIFO Control Block
Debug Control
DEBUG
FIFO Status
R
X
C
L
K
T
X
C
L
K
TXDIS, RXDIS
Interrupt IF
66 word X 32 bit
66 word X 32 bit
AHB Slave IF DMA Control IF
SCK
ECLK
WS