Cypress S6J3200 Series, Руководство пользователя

Страница: 626 / 1355

CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 625
[bit20:18] mdc_clock_division: MDC clock division
Set according to CLK_HAPP1B0 speed. These three bits determine the number, CLK_HAPP1B0 will
be divided by to generate MDC. MDC must not exceed 2.5 MHz (MDC is only active during MDIO read
and write operations)
Bits Description
000 divide by 8
001 divide by 16
010 divide by 32
011 divide by 48
100 divide by 64
101 divide by 96
110 divide by 128
111 divide by 224
[bit17] fcs_remove: FCS remove
Setting this bit will cause received frames to be written to memory without their frame check sequence
(last 4 bytes). The frame length indicated will be reduced by four bytes in this mode.
Bit Description
0 Disable
1 Enable
[bit16] length_field_error_frame_discard: Length field error frame discard
Setting this bit causes frames with a measured length shorter than the extracted length field (as
indicated by bytes 13 and 14 in a non-VLAN tagged frame) to be discarded. This only applies to frames
with a length field less than 0600
h
(1536
d
).
Bit Description
0 Disable
1 Enable
[bit15:14] receive_buffer_offset: Receive buffer offset
Indicates the number of bytes by which the received data is offset from the start of the receive buffer.
Bits Description
00 no offset
01 one byte offset
10 two byte offset
11 three byte offset
[bit13] pause_enable: Pause enable
Bit Description
0 Disable
1
Transmission will pause if a non zero 802.3 classic pause frame is received and PFC has not been
negotiated.