Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
582 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Receive Buffer
Offset
Configuration Bit 2
of Word 0
Receive_Buffer_Offset[1] Receive_Buffer_Offset[0]
Number of Bytes
Offset
1 1 0 6
1 1 1 7
If the start location of the buffer is offset the available length of the first buffer is reduced by the
corresponding number of bytes.
Table 3-2: Receive Buffer Descriptor Entry
Bit s Function
Word 0
31:3 Address [31:3] of beginning of buffer
2
Address [2] of beginning of buffer
or
In Extended Buffer Descriptor Mode, indicates a valid timestamp in the BD entry.
1 Wrap - marks last descriptor in receive buffer descriptor list.
0
Ownership - needs to be "0" for the Ethernet MAC to write data to the receive buffer. The
Ethernet MAC sets this to "1" once it has successfully written a frame to memory. Software has
to clear this bit before the buffer can be used again.
Word 1
31 Global all ones broadcast address detected.
30 Multicast hash match.
29 Unicast hash match.
28 External address match.
27 Unused.
26:25
Specific Address register match. Encoded as follows:
00 - Specific Address 1 register match (lowest priority)
01 - Specific Address 2 register match
10 - Specific Address 3 register match
11 - Specific Address 4 register match (highest priority)
If more than one specific address is matched only one of them is indicated with priority 4 down to
1.
24
This bit has a different meaning depending on whether RX checksum offloading is enabled
(ETHERNETn_network_configuration[24] = 1).
With RX checksum offloading disabled:
Type ID register match found, bit 22 and bit 23 indicate which Type ID register causes the match.
With RX checksum offloading enabled:
0 - The frame was not SNAP encoded and/or had a VLAN tag with the CFI bit set.
1 - The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit
not
set.