Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 31:Memory Protection Unit for AXI
1150 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.3.
MPU AXI Write Error Control Register (MPUXn_WERRC)
This is a read-only register that provides the software the control information of AXI transaction on AXI
master write address channel interface for which memory protection violation was detected. Software can
read this register to get privileged mode, burst length, burst size, and burst type information of AXI
transaction.
 MPUXn_WERRC
MPUXn_WERRC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0
A
W
S
IZ
E
[2
]
A
W
S
IZ
E
[1
]
A
W
S
IZ
E
[0
]
A
W
B
U
R
S
T
[1
]
A
W
B
U
R
S
T
[0
]
A
W
LE
N
[3
]
A
W
LE
N
[2
]
A
W
LE
N
[1
]
A
W
LE
N
[0
]
A
W
P
R
OTP
R
IV
A
W
MP
V
R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0
R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X 0
Bit Position Bit Field Name Bit Description
[31:16] read0
-
[15:11] read0
-
[10:8] AWSIZE
AXI Transaction Burst Size
This bit provides the status of AWSIZE[2:0] signals of AXI transaction for
which memory protection violation is detected.
[7:6] AWBURST
AXI Transaction Burst Type
This bit provides the status of AWBURST[1:0] signals of AXI transaction for
which memory protection violation is detected.
[5:2] AWLEN
AXI Transaction Burst Length
This bit provides the status of AWLEN[3:0] signals of AXI transaction for
which memory protection violation is detected.
[1] AWPROTPRIV
AXI Transaction Privileged Mode
This bit provides the status of AWPROT[0] signal of AXI transaction for which
memory protection violation is detected.
[0] AWMPV
AXI Write Memory Protection Violation
This bit indicates that memory protection violation is detected on AXI write
address channel.
Writing "1" to MPUXn_CTRL0:NMICL bit clears AWMPV bit.