Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 581
3.1.4.
Receive DMA Buffers
Received frames, optionally including FCS, are written to receive buffers located in system memory. The
receive buffer depth (rx_buf_size[7:0]) is programmable in the range of 64 bytes to 16 Kbytes in the DMA
Configuration register, with the default being 15.360 bytes.
The start location for each receive buffer is stored in system memory in a list of receive buffer descriptors
at an address location pointed to by the receive buffer queue pointer. The base address of the receive
buffer queue pointer must be configured by software using the receive buffer queue base address
registers (ETHERNETn_receive_q_ptr, ETHERNETn_receive_q1_ptr to ETHERNETn_receive_q3_ptr).
The number of words in each buffer descriptor (BD) is dependent on the operating mode. Each BD word
is defined as 32 bits. The first two words (Word 0 and Word 1) are used for all BD modes.
In Extended Buffer Descriptor mode (ETHERNETn_dma_config[28]:rx_bd_extended_mode_en = 1), two
BD words (Word 2 and Word 3) are added for timestamp capture if timestamp capture mode is enabled
(ETHERNETn_rx_bd_control[5:4]:rx_bd_ts_mode > 0
h
). There are therefore either two or four BD words
in each BD entry depending on the operating mode, and every BD entry will have the same number of
words. To summarize:
−
Every descriptor will be 64 bits wide when descriptor time capture mode is disabled.
−
Every descriptor will be 128 bits wide when descriptor time capture mode is enabled.
The following description details the functionality of Word 0 and Word 1. Each list entry consists of the
same first two words. The first (i.e. Word 0) contains the start location of the receive buffer and the
second (i.e. Word 1) the receive status. If the length of a receive frame exceeds the Ethernet MAC DMA
buffer length, the status word for the used buffer is written with zeroes except for the "start of frame" bit,
which is always set for the first buffer in a frame. Bit zero of the address field is written to "1" to show the
buffer has been used. The receive buffer manager then reads the location of the next receive buffer and
fills that with the next part of the received frame data. Receive buffers are filled until the frame is complete
and the final buffer descriptor entry table for details of the receive buffer descriptor list.
When using receive descriptor timestamp capture, bit 2 of Word 0 is used to indicate a valid timestamp
has been captured in the BD. The use of bit 2 for this purpose also necessitates the data buffer being
located on a 64-bit address boundary.
Each receive buffer start location is a word address. The start of the first buffer in a frame can be offset by
up to seven bytes depending on the value written to bits 15 and 14 of the Network Configuration register
(receive_buffer_offset[1:0]) and bit 2 of Word 0.
Table 3-1: Receive Buffer Byte Offset Configuration
Receive Buffer
Offset
Configuration Bit 2
of Word 0
Receive_Buffer_Offset[1] Receive_Buffer_Offset[0]
Number of Bytes
Offset
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5