Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 931
[bit13] MSMD : Master and Slave Mode Select
Master and Slave modes are set.
Bit Description
0 Slave operation
1 Master operation
[bit12] SBFN : Sub Frame Construction
Sub frame construction (number of sub frame) of the frame is specified.
Bit Description
0 1 Sub frame construction (only sub frame 0)
1 2 Sub frame construction (sub frame 0 and sub frame 1). Frame starts from 0th sub frame
[bit11] RHLL : Word Construction
Word construction of FIFO – 1 word (32 bits) or 2 half words (16 bits) – is specified.
It is considered to be used at protocol, such as MSB-justified.
Bit Description
0 32-bit FIFO word is handled as 1 word
1
32-bit FIFO word is handled as 2 half words at serial bus with dividing 16 bits each to low order and high
order. They are transferred by serial bus in order of low order, high order, low order, and high order. At
reception, 2 consecutive half words from serial bus are handled as low order and high order, and they are
put in 1 word (32 bits) to write to reception FIFO
[bit10] ECKM : Clock Selector
Clock frequency dividing is selected in master mode.
Bit Description
0 Internal clock is divided and output
1 External clock (ECLK)is divided and output
[bit9] BEXT : Bit Extension
When reception word length is shorter than the word length of FIFO (32 bits when RHLL is "0" and 16
bits when RHLL is "1"), extension mode of upper bit (word length of FIFO-reception word length) should
be set.
Bit Description
0 Extended by "0"
1
Extended by sign bit (if MSB of word/half word is "1", then it is extended by "1", if MSB is "0" then it is
extended by "0")