Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
292 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5.
Registers
The A/D converter contains registers to configure the operation of A/D conversion and to store the
converted values. It also contains registers to configure the range comparators and registers to control
and store the status of the pulse detection function. This section describes the registers of the A/D
Converter in details.
The suffix "n" in the register name indicates that the register is an instance "n" of the module.
Registers of A/D Converter
Logical channel related registers are:

A/D Channel Control Registers (ADC12Bn_CHCTRL0 to 63)

A/D Channel Status Registers (ADC12Bn_CHSTAT0 to 63)

A/D Conversion Data Registers (ADC12Bn_CD0 to 63)

Pulse Counter Control Registers (ADC12Bn_PCCTRL0 to 63)

A/D Conversion Done Interrupt Flags (ADC12Bn_CDONEIRQ0 to 1)

A/D Conversion Done Interrupt Enable Registers (ADC12Bn_CDONEIRQE0 to 1)

A/D Conversion Done Interrupt Clear Registers (ADC12Bn_CDONEIRQC0 to 1)

Group Interrupted Interrupt Flags (ADC12Bn_GRPIRQ0 to 1)

Group Interrupted Interrupt Enable Registers (ADC12Bn_GRPIRQE0 to 1)

Group Interrupted Interrupt Clear Registers (ADC12Bn_GRPIRQC0 to 1)

Range Comparator Interrupt Flags (ADC12Bn_RCIRQ0 to 1)

Range Comparator Interrupt Enable Registers (ADC12Bn_RCIRQE0 to 1)

Range Comparator Interrupt Clear Registers (ADC12Bn_RCIRQC0 to 1)

Pulse Counter Interrupt Flags (ADC12Bn_PCIRQ0 to 1)

Pulse Counter Interrupt Enable Registers (ADC12Bn_PCIRQE0 to 1)

Pulse Counter Interrupt Clear Registers (ADC12Bn_PCIRQC0 to 1)

A/D Channel Trigger Status Flags (ADC12Bn_TRGST0 to 1)

A/D Channel Trigger Status Clear Registers (ADC12Bn_TRGCL0 to 1)

A/D Channel Trigger Overrun Flags (ADC12Bn_TRGOR0 to 1)

A/D Channel Trigger Overrun Clear Registers (ADC12Bn_TRGORC0 to 1)

Range Comparator Over Threshold Flags (ADC12Bn_RCOTF0 to 1)
Global A/D Converter registers are:

Conversion Done DMA Select Registers (ADC12Bn_CDDS0 to 3)

A/D Converter Resumption Time Setting Register (ADC12Bn_RT)

A/D Converter Comparison Time Setting Register (ADC12Bn_CT)

A/D Converter Sampling Time Setting Registers (ADC12Bn_ST0 to 3)

A/D Converter Offset Compensation Setting Register (ADC12Bn_OCV)

A/D Converter Gain Compensation Setting Register (ADC12Bn_GCV)

A/D Converter Global Control Register (ADC12Bn_CTRL)

A/D Converter Global Status Register (ADC12Bn_STAT)

Range Comparator Upper Threshold Registers (ADC12Bn_RCOH0 to 7)

Range Comparator Lower Threshold Registers (ADC12Bn_RCOL0 to 7)

Full Range Comparator Upper Threshold Registers (ADC12Bn_FRCOH0 to 7)

Full Range Comparator Lower Threshold Registers (ADC12Bn_FRCOL0 to 7)
Multiple conversion logical channel related registers are:

A/D Multiple Conversion Channel Control Registers (ADC12Bn_MCCTRL0 to 3)

A/D Multiple Conversion Channel Status Registers (ADC12Bn_MCSTAT0 to 3)