Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 22:Media Local Bus Interface (MediaLB)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 869
In IO Mode, this bit is not used.
[bit4] STS : STS[4] : Buffer Error bit
When set, this bit indicates that either a transmit channel has detected a buffer underflow (e.g., attempted
to pop data from an empty buffer), or a receive channel has detected a buffer overflow (e.g., attempted to
push data onto a full buffer).
The setting of this bit generates a maskable channel interrupt to the system software. This bit is valid for
synchronous receive/transmit and isochronous receive (MLBn_CECRn:FCE = 0) channels only.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
[bit3] STS : STS[3]
This bit has different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is Current Buffer Start bit. When set, this bit indicates that the DMA controller has
started processing the Current Buffer. This bit is set after the contents of MLBn_CNBCRn have been
loaded into MLBn_CCBCRn, the MLBn_CSCRn:RDY bit has been cleared (for ping-pong buffering), and
hardware is available to accept the next buffer.
The setting of this bit generates a maskable channel interrupt to system software. This bit is valid for all
channel types.
In IO mode this is a Transmit Service Request bit. When set, it indicates that a transmit channel requests
service from the system software. Transmit service requests are issued if the number of valid quadlets in
the local channel buffer is less than or equal to MLBn_LCBCRn:TH[6:0].
The setting of this bit generates a maskable channel interrupt to the system software. This bit is valid for
all channel types.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
[bit2] STS : STS[2]
This bit has different interpretation depending on DMA-mode or IO-mode.
In DMA mode this is Current Buffer Done bit. When set, this bit indicates that the last quadlet from the last
packet (in the Current Buffer) has been successfully transmitted or received. The setting of this bit
generates a maskable channel interrupt to system software. This bit is valid for all channel types.
In IO mode this bit is the Receive Service Request bit. When set, this bit indicates that a receive channel
is requesting service from system software. Receive service requests are issued if the number of free
quadlets in the local channel buffer is less than or equal to MLBn_LCBCRn:TH[6:0]. The setting of this bit
generates a maskable channel interrupt to system software. This bit is valid for all channel types.
Write "1" to clear this bit. Writing "0" has no effect.
Once set, this bit holds until it is cleared by software.
[bit1] STS : STS[1] : Current Buffer Detect Break bit.
When set, this bit indicates that either a transmit channel has detected a receiver break response,
ReceiverBreak (0x70), or a receive channel has detected a transmitter break command, ControlBreak
(0x36) or AsyncBreak (0x26), while processing the Current Buffer. The setting of this bit generates a
maskable channel interrupt to system software. This bit is valid for asynchronous and control channels