Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 37:Major Changes
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1331
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
Sound
system clock
47 - 57
Notes:
- The configuration of the maximum clock
frequency above should satisfy the values
specified in Datasheet.
- The frequency of CLK_CD5 and
CLK_CD5A0 should satisfy the following
conditions.
- CLK_CD5 = 240MHz or 120MHz.
- CLK_CD5A0 = 120MHz.
#135
Clock
configuration
47 - 55
Registers of INDICATOR PWM and
LCDE: CLK_SYSC0P: SSCG0
Registers of LCDC: CLK_LCP1A: PPL0
or SSCG0
#159
PLL/SSCG
maximum
frequency
47 - 56
Note:
−
The frequency of PLLout (output of
PLL/SSCG PLL multiplier circuit) should
be 800MHz or less.
#165
Source clock
list
47 - 56
(Source Clock - Local Clock List is
added.)
#312
Area of
SWDT
(Traveo PF)
58
B030_8000 B03F_FFFF || SYSC2 ||
SWDT
68
B030_8000 B03F_FFFF || SYSC1 ||
SWDT
#161
Base address
map
58 - 68
An address of a certain register can be
specified as below.
−
Base address
Look for the base address X of the
function from the base address map
below.
−
Offset address
Look for the offset address Y of the
register from the offset address list which
is described in the chapter of the function.
Each function chapter has offset address
list or its information.
−
Specify
The register address can be specified
as X + Y.
#199