Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 18:Sound Generator
414 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.3.
Relation between the PWM Cycle Data Register (SGPCR) and PWM Cycle
This section describes the relation between the PWM Cycle Data Register (SGPCR) and PWM cycle.
Figure 3
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4 Relation between the PWM Cycle Data Register (SGPCR) and PWM Cycle
The length of a PWM cycle is programmable in the PWM Cycle Data Register (SGPCR). This length is
based on the count of input clock, and defined as "PWM Cycle Data Register [SGPCR] + 1". The input
clock is created by dividing the bus clock.
The PWM cycle is a reference clock for a tone pulse signal (or a mixed signal of the tone pulse signal and
a PWM pulse signal), and a PWM pulse signal.
To generate the same sound output both by the bus clock at 16 MHz and 40 MHz, for example, it can be
made by changing the values of the PWM Cycle Data Register (SGPCR) and the Amplitude Data
Register (SGAR). Because the bus clock proportion of 16 MHz and 40 MHz is 1:2.5, the same sound can
be made by setting the values of these two registers to 1:2.5.
SGAR
0x007F
1 PWM cycle
(256 input clock cycles)
(128 input clock cycles)
SGPCR
0x00FF
Bus clock (BCLK): 16MHz
SGAR
0x013F
1 PWM cycle
(640 input clock cycles)
(320 input clock cycles)
SGPCR
0x027F
Bus clock(BCLK): 40MHz
1 PWM cycle
(256 input clock cycles)
1 PWM cycle
(640 input clock cycles)