Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 26:PCMPWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 989
3.4.
Interrupts
The PCMPWM module interrupts are controlled by three registers: the Interrupt Enable Register
(PCMPWMi_INTREN), the Interrupt Status Register (PCMPWMi_INTRSTAT) and the Interrupt Clear
Register (PCMPWMi_INTRCLR). After reset all interrupts are disabled. If an interrupt is to be used, it
must be first enabled. The current status of an interrupt may be checked at any time in the Interrupt
Status Register. The Interrupt Status Register contents are independent of the enable status of the
interrupts. I.e. the Interrupt Status Bits are not masked by the Interrupt Enable Register.
If an interrupt has occurred, it can be reset by the Interrupt Clear Register. Writing a logic 1 to a bit in the
Interrupt Clear Register clears the corresponding interrupt line as well as the interrupt status bit.
1. DMA Block Error Interrupt
This interrupt indicates an error case when the DMA tries to transfer more data to the FIFO buffer than
configured by PCMPWMi_CONTROL:FEST + 1.
2. FIFO Buffer Under-Run Error Interrupt
This interrupt indicates an under-run of the FIFO buffer for PCM data samples. I.e. the PCM to PWM
conversion has tried to read a PCM data sample from the FIFO buffer when it was empty. Instead of a
new PCM data sample the PCM to PWM conversion uses the last PCM value instead.
3. FIFO Buffer Overflow Error Interrupt
This interrupt indicates the CPU has tried to write another PCM data sample to the FIFO buffer when it
was already completely filled.
4. Data Request Interrupt
This interrupt indicates there is at least space for another FEST + 1 PCM data samples in the FIFO
buffer. I.e. the PCMPWM module asserts the interrupt request when a read from the FIFO buffer frees
up another PCM samples slot, so that there are FEST + 1free entries in total.
3.5.
Dead Timer Operation
In full H-Bridge mode, the 16-bit counter is compared in each count period CP with the value from the
function minimum(duty, cycle) (this is the falling edge or the end of the PWM cycle). If the two values
match, a down counter loaded with PCMPWMi_CONTROL:DTVAL starts to decrement with every clock
cycle of the 16-bit counter. As long as the down counter is not zero, the opposite phase of the PWM
outputs is masked with inactive values. Opposite phase in this case means:
−
If the PCM data sample of count period CP is positive, then output signals PCMPWM_i_BL/BH are
masked, although this doesn't happen in usual setup.
−
If the PCM data sample of count period CP is negative, then output signals PCMPWM_i_AL/AH are
masked, although this doesn't happen in usual setup.