Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 18:Sound Generator
456 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.9.
DMA Transfer Intermediate Register (SGDMAR)
The DMA Transfer Intermediate Register (SGDMAR) is available in DMA transfer, and works as a window
to access several registers. The details are described in "3.4 Relation between the DMA Transfer Update
Enable Register (SGDER) and DMA ".
bit 31 30 29 28 27 26 25 24
Field SGDMAR[31:24]
Attribute W
Initial value 0x00
bit 23 22 21 20 19 18 17 16
Field SGDMAR[23:16]
Attribute W
Initial value 0x00
bit 15 14 13 12 11 10 9 8
Field SGDMAR[15:8]
Attribute W
Initial value 0x00
bit 7 6 5 4 3 2 1 0
Field SGDMAR[7:0]
Attribute W
Initial value 0x00
[bit31:0] SGDMAR : DMA Transfer data bits
This register is used to write the following registers:
-
Amplitude Data Register (SGAR)
-
Frequency Data Register (SGFR)
-
Tone Output Number Register (SGNR)
-
Time Cycle Register (SGTCR)
-
Increase and Decrease Data Register (SGIDR)
-
PWM Cycle Data Register (SGPCR)
The details are described in "3.4 Relation between the DMA Transfer Update Enable Register
(SGDER) and DMA ".
The read value is always 0x00000000.
Notes:
−
If the number of DMA transfer is greater than
"the number determined by the DMA Transfer Update Enable Register (SGDER)",
the value of this register is updated.
−
When in reading corresponding registers (not through this register), please make sure the setting
of "DMA Transfer Update Enable Register (SGDER)" is available for the target registers.