Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 23:Stereo Audio DAC
886 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.11.
Output Stop Control of Analog DAC
The procedure for stopping the output data of analog DAC is below.
1) Write a "1" into the INIT bit of the DACR register.
2) FIFO is reset by writing "1" in FLUSH bit of the DAFLUSH register.
FIFO is reset by writing "1" in FLUSH bit, and the DAC_DATA_REQ_IRQ and DAC_DMA_REQ
interrupt are issued.
3) Write a "0" into the INIT bit of the DACR register. As a result, the output of analog DAC is restarted.
When FIFO FLUSH is not used, it restarts by using the data stored in FIFO. However, the first data that was
stored in the FIFO are discarded.
3.12.
Bridge-tied Load (BTL)
The Stereo Audio DAC mounts the method of connection by Bridge-tied load(BTL). When BTL is used,
output L and R of Audio DAC become the signal outputs with the phase difference of 180°.
It is necessary to reverse the polarity of the upper 16 bits (LDATA) by the DPCR register setting when BTL
is applied or to reverse the polarity of the lower 16bits (RDATA). Concretely, the phase of the input signal
is reversed by writing 01b or 10b in the DPCR register.
Table 7 AHB DATA (Input DATA)Format
31 16 15 0
The upper 16bits (LDATA) The lower 16bits (RDATA)
Left-Chanel Right-Chanel
Notes:
−
BTL assumes the case when input data 32bit to Audio DAC is monaural (31:16 and 15:0 are
equal). The effect that monaural BTL expects is not achieved though it operates even when 32bit
stereo data of L ≠ R is input.
−
Do not set the value of the DPCR register to 00b or 11b.
Because the amplitude is counterbalanced when connecting it with one speaker