CHAPTER 7:Memory and Base Address Map
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
65
Start
Address
End
Address
Group
Part
5021_4800
5021_4FFF
Graphic subsystem
(AppS #8)
Reserved
5021_5000
5021_53FF
MPU_AXI (3D_Graphics_Core_Write Port A)
5021_5400
5021_57FF
MPU_AXI (3D_Graphics_Core_Write Port B)
5021_5800
5021_5BFF
MPU_AXI (3D_Graphics_Core_Write Port C)
5021_5C00
5027_FFFF
Reserved
5028_0000
5028_0FFF
Hyper Bus ch.1 Control Register
5028_1000
5028_1FFF
Hyper Bus ch.2 Control Register
5028_2000
502F_FFFF
Reserved
5030_0000
5030_FFFF
3D Graphics Core
5031_0000
503F_FFFF
Reserved
5040_0000
504F_FFFF
High Performance Bus Matrix
5050_0000
5FFF_FFFF
Reserved
6000_0000
7FFF_FFFF
Reserved
Reserved
8000_0000
8FFF_FFFF
HSSPI0_MEMORY
DDRHSSPI for CPU area
9000_0000
9FFF_FFFF
HSSPI1_MEMORY(Apps#11)
Memory for Hyper Bus ch.0
A000_0000
AFFF_FFFF
Reserved
Reserved
B000_0000
B7FF_FFFF
Peri area
Peri area
B800_0000
B802_87FF
Apps#3
Expansion area
B802_8800
BFFF_FFFF
Reserved
Reserved
C000_0000
EFFF_FFFF
Reserved
Reserved
F000_0000
FFFE_DFFF
BootROM/ERRCFG area
Reserved
FFFE_E000
FFFE_EFFF
ERRCFG
FFFE_F000
FFFE_FFFF
FFFF_0000
FFFF_FFFF
BootROM
Notes:
−
The sector configuration and end address of FLASH and RAM are described in the chapter of
TCRAM, TCFLASH, and WorkFLASH of Traveo platform hardware manual.
Содержание S6J3200 Series
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