Cypress S6J3200 Series, Руководство пользователя

Страница: 1189 / 1355

CHAPTER 33:Graphics Subsystem
1188 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
2.7.
Video RAM
The Video RAM block has the features listed below.

2MB embedded SRAM. And it is consists of memory 8 banks.

64-bit data width => 1.600 MB/s peak bandwidth per port @ 200 MHz bus speed

It has four access ports that all share the same address range; fixed mapping of all masters to one of
these ports:
−
write port: All write masters
−
1st read port: All non Display Controller read masters of the 2D Graphics Core and Main System
(bandwidth sensitive)
−
2nd read port: All Display Controller read masters of the 2D Graphics Core (bandwidth critical)
−
3rd read port: All read masters of the 3D Graphics Core.

Configurable priority for each port or Round-Robin arbitration.

Arbitration not on burst, but single memory access level => can guarantee max possible bandwidth to
certain VRAM ports

Memory is separated into 8 banks with interleaved address access. This allows
−
Full bandwidth on all ports in parallel for ordered access patterns, i.e. 6,400 MB/s peak bandwidth
in total (drops for random access patterns)
−
Operation of individual banks at half the bus clock speed only.

Optionally ECC (Error Checking and Correction) for sub sections of the VRAM.
2.8.
DDR High-Speed SPI
For the detailed information for the DDR High-Speed SPI interface, refer to [2]
2.9.
HyperBus
[TM]
Interface
For the detailed information for the HyperBus [TM] interface, refer to [4].