Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 695
4.41.
Octets Transmitted Bottom Register
(ETHERNETn_octets_txed_bottom)
Description of Octets Transmitted [31:0] register is shown. When reading the Octets Transmitted registers,
bits [31:0] (ETHERNETn_octets_txed_bottom) should be read prior to bits [47:32]
(ETHERNETn_octets_txed_top) to ensure reliable operation.
REGISTER_NAME ETHERNETn_octets_txed_bottom
OFFSET 0x100
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME count[31:24]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME count[23:16]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME count[15:8]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME count[7:0]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:0] count: Transmitted octets in frame without errors [31:0]
The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read
through two registers (ETHERNETn_octets_txed_top and ETHERNETn_octets_txed_bottom). This
count does not include octets from automatically generated pause frames.