LeCroy DDA 7 Zi series, Руководство оператора

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Operator's Manual
WP700Zi-OM-E-RevA
444
Front Side Bus (FSB)
Introduction to FSB
Front Side Bus is also known as the processor bus, memory bus, or system bus. The FSB connects the
processors to the main memory, and is used to connect to other resources within the computer. The FSB can
range from speeds of 66 MHz, 133 MHz, 100 MHz, 266 MHz, 400 MHz, and higher.
The FSB speed can generally be set either using the system BIOS or with jumpers located on the computer
motherboard. FSB can accommodate one or two CPUs. This section of the manual describes single CPU
operation.
FSB Theory of Operation
There are three sub-buses in the FSB: data bus, address bus, and common clock bus. All these buses are
bidirectional; information can flow in either direction. The direction of the bit flow will be determined by the relative
position of the high-to-low transition in the strobe pins (address, data or clock) when simultaneously probed at
both ends of the applicable bus. For example, when signal A transition is delayed relative to signal B transition,
this means that B is the transmitter and A is the receiver. The bus clock (BCLK) signal is formed by a differential
pair, BCLK0 and BCLK1, running at 533 MHz. This is the trigger signal for the bit transactions, with the strobe
signals as the qualifiers for the actual bit transfers.
Data Bus Characteristics (Refer to the Following Figure)
x
During every period of BCLK, 4 bits are sent or there's an idle state: high voltage on both strobes and
relevant data pins.
x
Bit transfers occur in quad multiples of bits only (4, 8, 12…).
x
Data Strobe positive (DSTBp#) samples bits 0 and 2 on consecutive falling edges
x
Data Strobe negative (DSTBn#) samples bits 1 and 3 on consecutive falling edges
Figure 5-49. Data Bus Timing Diagram ©Intel Corporation.
Address Bus Characteristics (Refer to the Following Figure)
x
During every period of BCLK, 2 bits are sent or there's an idle state (high voltage on both strobes and
relevant data).
x
Bit transfers occur in double multiples of bits only (2, 4, 6…).
x
There's sampling of address bits on both falling and rising edges of ADSTB
x
Falling edge (ASTB#) samples address bit 0