LeCroy DDA 7 Zi series, Руководство оператора

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WavePro 7Zi
397
WP700Zi-OM-E-RevA
1. Place a check in the PLL On checkbox to enable it.
2. Touch inside the PLL Type field to select the type of PLL to be used in the clock recovery function. The
choices are FC Golden , PCI Express Gen1 , PCI-Express G2 A 3dBpk 16 MHz fc , PCI-Express G2 B
3dBpk 8 MHz fc , PCI Express G2 C 1dBpk 5 MHz fc , DVI , FB-DIMM , and Custom .
A. FC Golden is the default selection and implements the “golden” PLL as defined in the Fibrechannel
specification. By default, the golden PLL is set to a cutoff frequency of 1/1667 times the bit rate of the
signal under test. This ratio can be adjusted from 1/10 to 1/1e6.
B. The PCI Express PLL uses a filter that approximates the PCI-SIG compliance requirement. The PCI-
SIG compliance procedure describes a processing algorithm that measures the average bit rate over
3500 consecutive unit intervals (UI or bit intervals). The 250 UI in the center of this 3500 UI window are
then processed using the average bit rate as a reference clock. The 3500 UI window is then shifted by
some number of UI and the process is repeated. Measurement continues until the end of the acquired
data record is reached. The PCI Express PLL selection in the SDA models the sliding 3500 UI clock
recovery and 250 UI processing windows using a digital low-pass filter whose cutoff frequency is
approximately 1.5 MHz.
C. The DVI selection follows the requirements of the DVI (Digital Video Interactive) and HDMI (High
Definition Multimedia Interface) specifications. These specifications call out a clock recovery function
that has a single-pole PLL loop response with a cutoff of 4 MHz.
D. The Custom selection allows you to select either a first or second order loop response. The first order
response allows you to select a pole frequency that sets the PLL cutoff, and a zero frequency that must
be higher than the pole frequency that limits the stop-band attenuation.
The second order PLL allows you to select the natural frequency and damping factor. The damping
factor determines the transient behavior of the phase locked loop and is variable from 2 to 0.5. A
damping factor above 0.707 results in an under-damped response in which the PLL will over-correct to
a sudden change in frequency, but will react more quickly to the change. A damping factor below 0.707
will give an under-damped response that will react more slowly to sudden changes in frequency, but
will not over-correct.
The default value of 0.707 represents a critically damped response that will give the fastest reaction
time without over-correcting.
The second order PLL with a damping factor of 0.707 is specified in the serial ATA generation II
document. This type of PLL is also very useful for measuring signals with spread-spectrum clocking
because it can accurately track and remove the low-frequency clock spreading while allowing the
signal jitter to be measured. The natural frequency is somewhat lower than the actual 3 dB cutoff
frequency given by the following equation:
The quantity is the damping factor, and is the natural frequency. For a damping factor of
0.707, this relationship is f
c
= 2.06 f
n
.
3. Settings for the FC Golden PLL: Touch inside the Cutoff Divisor [The PLL cutoff divisor is the value by
which the bit rate is divided to compute the cutoff frequency for the loop bandwidth of the clock recovery
operation for sequential eye pattern, jitter, and bit error rate functions. This control is variable from 10 to