LeCroy DDA 7 Zi series, Руководство оператора

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Operator's Manual
WP700Zi-OM-E-RevA
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level field and enter a percentage value, using the pop-up keypad. The level is automatically set to the
selected percentage on each acquisition.
Note: The absolute level setting should be used for jitter measurements over several acquisitions because the
relative setting can potentially remove jitter by tracking slowly, thereby varying level shifts that could occur
between acquisitions.
5. Touch inside the Signal Type field and select a standard signal type from the pop-up menu. The signal
type defines the compliance masks and bit rates for the selected standard.
If you selected Custom from the Signal Type menu, touch inside the Bit Rate field and enter a bit rate,
using the pop-up keypad. By touching the Find Bit Rate button, you can have the bit rate determined
automatically. This button is also available when a standard data type is selected.
6. The Pattern Length [The number of bits in the pattern.] control sets the repetition length of the data
pattern in the signal under test. Serial data signals generally transmit a repeating data pattern of some sort.
For example a PRBS7 pattern repeats every 127 bits while a K28.5 repeats every 20 bits. Enter the pattern
length in the
Pattern Length control. Alternatively, the SDA can automatically find the pattern length by
means of the Find Pattern Length button. The Find Pattern Length button determines the pattern
repetition length (if any) in the current acquisition and sets the Pattern length field to this value. The Pj
measurement uses the pattern length value to determine which peaks in the jitter spectrum are caused by
the pattern repetition. An incorrect value in the Pattern Length control will result in overestimating the Pj
and, as a result, underestimating the random jitter.
7. The Multiplier , Deskew , and Clock Slope controls adjust the positioning of the clock relative to the data
edges when an external clock source is selected. These controls are active only if the Recover clock
checkbox is left unchecked. The Multiplier control is used when a sub-rate clock is applied. For example, if
a clock signal at 1/10 the bit rate is used, the Multiplier control should be set to 10 in order to get a single
eye pattern on the display.
The Deskew control enables positioning of the clock edges relative to the data signal. It shifts the clock
signal relative to the data signal.
A clock signal goes through one complete cycle during each bit interval. The edge timing can be measured
relative to the rising or falling slope of the clock by means of the
Clock Slope setting.
The Tx Density control indicates the ratio of transitions in the data record to the total number of bits in the
signal. Normally, an NRZ data stream does not have transitions during every bit interval. For example, there
are cases where adjacent 1 or 0 values exist. On average, approximately 50% of the bit intervals have
transitions so the Tx density is 500e-3. The actual acquired data set may have a transition density different
from 50%, however. The total jitter measurement uses this transition density to normalize the measured
histogram into a pdf[probability density function] . Many instruments simply assume 50% when performing
this normalization which can lead to errors. These errors are eliminated in the SDA through the use of the
measured transition density in the normalization process. The Tx density is automatically measured when
the
Find Pattern Length button is pressed.
Note: If the pattern length exceeds the number of bits in the acquired waveform or there is no repeating pattern
present, the control will indicate a value equal to the total number of bits in the current acquisition. In this case,
the pattern length control should be set to 2 so that the Pj will not be underestimated
Note: An incorrect pattern length will result in an overestimated value for Pj. This overestimate will cause Dj to
read high and Rj to read low.
PLL Setup
The PLL Settings dialog contains the controls to set the type and bandwidth of the digital PLL used in the jitter,
eye pattern, and bit error rate tests. The PLL bandwidth limits the response of the recovered clock to high rate
variations in the data rate. For example, a PLL bandwidth of 750 kHz will allow the recovered clock to track
frequency variations below this rate, thereby removing their effect from jitter and eye pattern measurements. The
software PLL implemented in the SDA allows you to choose among four types of PLL.
The selected PLL is applied to either the data stream under test or the selected clock source when the PLL On
control is checked. The PLL recovers a reference clock from the selected source, which is used by all subsequent
SDA measurements (jitter, eye pattern, and, bit error rate).