WavePro 7Zi
445
WP700Zi-OM-E-RevA
x
Rising edge (ASTB#) samples address bit 1
Figure 5-50. Address Bus Timing Diagram ©Intel Corporation.
Common Clock Bus Characteristics (Refer to the Following Figure)
x
During every period of BCLK, 1 bit is sent or there's an idle state meaning high voltage on the signal.
x
BCLK is a differential signal.
Figure 5-51. Common Clock Bus Timing Diagram © Intel Corporation.
Transition/Non-Transition Eye Diagram
A dual display eye diagram is formed with bits that are of non-changing polarity (non-transition) and changing
polarity (transition). This display mode is useful for those serial data standards that utilize mask testing for both
types of bit sequences (PCI Express and FB-DIMM Point to Point).
Содержание DDA 7 Zi series
Страница 1: ...Operator s Manual WavePro SDA and DDA 7 Zi Series Oscilloscopes ...
Страница 2: ... L R R H HUD RU D D ...
Страница 41: ...Operator s Manual WP700Zi OM E RevA 40 The detachable WavePro Zi front panel ...
Страница 376: ...WavePro 7Zi 375 WP700Zi OM E RevA Absolute Offset Relative ...
Страница 439: ...Operator s Manual WP700Zi OM E RevA 438 ...
Страница 440: ...WavePro 7Zi 439 WP700Zi OM E RevA ...
Страница 544: ...Thank you for purchasing a WavePro SDA or DDA 7 Zi Oscilloscope ...