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RS_Color liquid crystal display controller (CLCD)

RM0082

Doc ID 018672 Rev 1

33.7 Interrupts

There are five interrupts generated by the CLCD. The following are individual maskable
active HIGH interrupts:

●

CLCDMBEINTR

●

CLCDVCOMPINTR

●

CLCDLNBUINTR

●

CLCDFUFINTR

The output is a combined to give a single interrupt CLCDINTR. Each of the four individual
maskable interrupts is enabled or disabled by changing the mask bits in the LCDIMSC
Register.

The status of the individual interrupt sources can be read from the LCDRIS Register.

33.7.1 CLCDMBEINTR

The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signalled to it. On completion of the respective interrupt service routine, the
master bus error interrupt can be cleared by writing a logic ‘1’ to the MBERROR bit within
the LCDICR Register. This action releases the master interface from its ERROR state to the
start of FRAME state, enabling a fresh frame of data display to be initiated.

33.7.2 LCDVCOMPINTR

The vertical compare interrupt is asserted when one of four vertical display regions, elected
using the Control Register, is reached. The interrupt can be made to occur at the start of:

●

vertical synchronization

●

back porch

●

active video

●

front porch.

It is possible to clear the interrupt by writing a logic ‘1’ to the VComp bit in the LCDICR
Register.

33.7.3 CLCDLNBUINTR

The LCD next base address update interrupt is asserted when either the LCDUPBASE or
the LCDLPBASE values are transferred to the LCDUPCURR or LCDLPCURR incrementors
respectively. This signals to the system that it is safe to update the LCDUPBASE or the
LCDLPBASE Registers with new frame base addresses if required.

Table 697: PCELLIDID3 register bit assignments

Bit

Name

Reset Value

Description

[31:08]

-

-

Reserved, read as zero

[07:00]

PCELLIDID3

8’hB1

These bits read back as 0xB1

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Summary of Contents for SPEAr300

Page 1: ...n chip peripherals Each member of the SPEAr3xx family has a specific set of IPs implemented in its Reconfigurable Array Subsystem RAS In the SPEAr300 the following IPs are implemented in the RAS FSMC...

Page 2: ...rchitecture overview 59 4 3 1 Core architecture 59 4 4 CPU subsystem 60 4 5 Multilayer bus matrix 60 4 6 Dynamic memory controller 60 4 7 Basic subsystem 61 4 8 High speed connectivity subsystem 61 4...

Page 3: ...89 8 1 Overview 89 8 2 Block diagram 89 8 3 Main functions description 90 8 3 1 Interrupt request logic 90 8 3 2 Non vectored FIQ interrupt logic 90 8 3 3 Non vectored IRQ interrupt logic 91 8 3 4 Ve...

Page 4: ...21 Identification registers 101 8 6 22 VICPCELLID0 register 101 8 6 23 VICPCELLID1 register 101 8 6 24 VICPCELLID2 register 102 8 6 25 VICPCELLID3 register 102 9 Bus interconnection matrix 103 9 1 IC...

Page 5: ...checking 140 10 8 2 Mobile devices DQS 141 10 8 3 Half datapath option 141 10 8 4 User defined registers 142 10 9 Address mapping 142 10 9 1 DDR SDRAM address mapping options 142 10 9 2 Maximum addre...

Page 6: ...13 27 MEM22_CTL register 167 10 13 28 MEM23_CTL register 167 10 13 29 MEM24_CTL register 168 10 13 30 MEM25_CTL register 168 10 13 31 MEM26_CTL register 169 10 13 32 MEM27_CTL register 169 10 13 33 M...

Page 7: ...10 13 64 MEM62_CTL MEM63_CTL MEM64_CTL register 180 10 13 65 MEM65_CTL register 180 10 13 66 MEM66_CTL register 180 10 13 67 MEM67_CTL register 180 10 13 68 MEM68_CTL register 181 10 13 69 MEM 69 97 _...

Page 8: ...CFG_CTR register 213 12 4 4 DIAG_CFG_CTR register 216 12 4 5 PLL 1 2_CTR registers 218 12 4 6 PLL1 2_FRQ registers 220 12 4 7 PLL1 2_MOD registers 221 12 4 8 PLL_CLK_CFG register 222 12 4 9 CORE_CLK_C...

Page 9: ...RES register 257 12 4 38 BIST5_RSLT_REG register Reserved 258 12 4 39 Diagnostic functionality 260 12 4 40 SYSERR_CFG_CTR register 260 12 4 41 USB_TUN_PRM register 262 12 4 42 PLGPIOn_PAD_PRG Register...

Page 10: ...6 4 SSPCR0 register 278 13 6 5 SSPCR1 register 279 13 6 6 SSPDR register 279 13 6 7 SSPSR register 280 13 6 8 SSPCPSR register 280 13 6 9 SSPIMSC register 281 13 6 10 SSPRIS register 281 13 6 11 SSPM...

Page 11: ...ption 293 14 4 3 SCCTRL register 293 14 4 4 SCSYSSTAT register 294 14 4 5 SCIMCTRL register 295 14 4 6 SCIMSTAT register 295 14 4 7 SCXTALCTRL register 296 14 4 8 SCPLLCTRL register 296 15 BS_Serial m...

Page 12: ...Main functions description 314 16 3 1 AMBA APB interface 314 16 3 2 Free running counter 314 16 4 Clock signals 314 16 5 Programming model 315 16 5 1 Register map 315 16 5 2 Register description 316 1...

Page 13: ...6 18 3 2 Interrupt detection logic 326 18 3 3 Mode control 327 18 4 How to 327 18 4 1 Read from and write to input output lines 327 18 4 2 Control interrupt generation 327 18 5 Programming model 328 1...

Page 14: ...ter 341 19 7 7 DMACIntErrClr register 341 19 7 8 DMACRawIntTCStatus register 342 19 7 9 DMACRawIntErrorStatus register 342 19 7 10 DMACEnbldChns register 342 19 7 11 DMACSoftBReq register 343 19 7 12...

Page 15: ...360 21 4 4 Channel 360 21 4 5 CCM Coupling Chaining module 361 21 5 Processing overview 362 21 6 Programming model 362 21 6 1 Register map 362 21 6 2 System registers C3_SYS 363 21 6 3 Register confi...

Page 16: ...385 21 8 10 Register set 386 21 8 11 DES register description 386 21 8 12 Data input output registers DES_DATAINOUT 386 21 8 13 Feedback registers DES_FEEDBACK 387 21 8 14 Control and status register...

Page 17: ...ion 397 21 11 9 SAVE 397 21 11 10 RESTORE 397 21 11 11 HMAC instruction 398 21 11 12 HMAC MD5 SHA1 instructions 398 21 11 13 INIT 398 21 11 14 APPEND 398 21 11 15 END 399 21 11 16 HMAC CONTEXT instruc...

Page 18: ...configuration 417 22 6 Programming model 417 22 6 1 External pin connections 417 22 6 2 UHC interrupts 417 22 6 3 Register map 418 22 6 4 Register descriptions of EHCI 421 22 6 5 HCCAPBASE register 4...

Page 19: ...HcControlCurrentED register 449 22 6 36 HcBulkHeadED register 450 22 6 37 HcBulkCurrentED register 450 22 6 38 HcDoneHead register 451 22 6 39 Frame counter partition 451 22 6 40 HcFmInterval register...

Page 20: ...5 1 SETUP data memory structure 478 23 5 2 OUT data memory structure 479 23 5 3 IN data memory structure 481 23 6 Operation modes In DMA mode 484 23 6 1 Packet per buffer mode 484 23 6 2 Buffer fill m...

Page 21: ...HB master interface 506 24 3 3 DMA controller 507 24 3 4 Transmit and receive FIFO 507 24 3 5 MAC management counters 507 24 3 6 Power management module PMT 508 24 4 DMA descriptors 508 24 4 1 Transmi...

Page 22: ...ster6 MAC 541 24 7 23 VLAN tag register Register7 MAC 543 24 7 24 Wake up frame filter register Register10 MAC 543 24 7 25 PMT control and status register Register11 MAC 544 24 7 26 Interrupt status r...

Page 23: ...ster 565 25 4 11 JPGC bust count beforeInit 565 25 4 12 DMAC registers 565 25 4 13 JPGCFifoIn register 565 25 4 14 JPGCFifoOut register 566 25 4 15 JPGCqmem memory 566 25 4 16 JPGChuffmin memory 567 2...

Page 24: ...5 15 IrDA_MIS register 585 26 5 16 IrDA_ICR register 586 26 5 17 IrDA_ISR register 587 26 5 18 IrDA_DMA register 587 27 LS_Universal asynchronous receiver transmitter UART 589 27 1 Overview 589 27 2...

Page 25: ...model 619 28 6 1 External pin connections 619 28 6 2 Register map 619 28 6 3 IC_CON register 0x000 621 28 6 4 IC_TAR register 0x004 623 28 6 5 IC_SAR register 0x008 624 28 6 6 IC_HS_MADDR register 0x...

Page 26: ...643 29 3 Operating sequence 644 29 3 1 Normal mode 644 29 3 2 Enhanced mode 644 29 4 Programming model 645 29 4 1 External pin connection 645 29 5 Register description 646 29 5 1 ADC_STATUS_REG regist...

Page 27: ...662 31 1 Overview 662 31 2 Functional description 663 31 2 1 Block diagram 663 31 3 Description 663 31 3 1 AHB interface 663 31 3 2 NAND flash controller 663 31 3 3 Asynchronous SRAM and NOR parallel...

Page 28: ...9 32 7 6 CMD register 701 32 7 7 RESP i registers 702 32 7 8 Buf data port register 703 32 7 9 PRSTATE register 703 32 7 10 HOSTCTRL register 707 32 7 11 PWRCTL register 708 32 7 12 BLKGAPCTRL registe...

Page 29: ...panel signal multiplexing details 738 33 5 Main functions description 740 33 5 1 AHB slave interface 740 33 5 2 AHB master interface 740 33 5 3 Dual DMA FIFOs and associated control logic 741 33 5 4 P...

Page 30: ...762 33 7 1 CLCDMBEINTR 762 33 7 2 LCDVCOMPINTR 762 33 7 3 CLCDLNBUINTR 762 33 7 4 CLCDFUFINTR 763 33 7 5 LCD powering up and powering down sequence support 763 33 8 CLCD clock scheme 764 34 RS_Teleco...

Page 31: ...34 6 11 GPIOtt register 792 34 6 12 PERS_time register 792 34 6 13 PERS_data register 792 34 6 14 TDM_timeslot_NBR register 792 34 6 15 TDM_frame_NBR register 793 34 6 16 TDM_SYNC_GEN register 793 34...

Page 32: ...37 2 4 NORMAL 819 37 3 Dynamic frequency scaling 820 37 4 Dynamic clock switching 820 37 5 Combining frequency scaling and clock switching techniques 821 37 6 Statiscally frequency selection and cloc...

Page 33: ...er and U boot Header 829 38 4 5 X Loader and U boot authentication 829 38 5 Boot flows 830 38 5 1 Serial NOR Flash boot 831 38 5 2 NAND Flash boot 832 38 5 3 USB boot 834 38 5 4 Serial UART Boot 839 3...

Page 34: ...ol registers summary 93 Table 26 VIC vector address registers summary 94 Table 27 VIC interrupt vector control registers summary 95 Table 28 VIC identification registers summary 95 Table 29 VICIRQSTAT...

Page 35: ...2 333 MHz cl5 initialization table 146 Table 75 MT46H6M16LF 6 Low Power DDR 166 MHz cl3 initialization table 147 Table 76 Parameter size to mapping conditions 149 Table 77 Registers overview 150 Table...

Page 36: ...gnments 176 Table 125 MEM49_CTL register bit assignments 177 Table 126 MEM50_CTL register bit assignments 177 Table 127 MEM51_CTL register bit assignments 177 Table 128 MEM52_CTL MEM53_CTL register bi...

Page 37: ...1 Table 177 USB2_PHY_CFG register bit assignments 242 Table 178 MAC_CFG_CTR register bit assignments 242 Table 179 Powerdown_CFG_CTR register bit assignments 243 Table 180 COMPSSTL_1V8_CFG DDR_2V5_COM...

Page 38: ...4 Table 229 PCELLID2 register bit assignment 284 Table 230 PCELLID3 register bit assignment 284 Table 231 System controller control and status registers summary 292 Table 232 System controller identif...

Page 39: ...s summary 339 Table 282 DMACIntStatus register bit assignments 340 Table 283 DMACIntTCStatus register bit assignments 340 Table 284 DMACIntTCClear register bit assignments 341 Table 285 DMA ClntErrorS...

Page 40: ...it aa encoding 396 Table 334 HASH APPEND Instruction bit encoding 396 Table 335 HASH END Instruction bit encoding 397 Table 336 HASH CONTEXT SAVE Instruction bit encoding 397 Table 337 HASH CONTEXT RE...

Page 41: ...nts 457 Table 387 HcRhPortStatus register bit assignments 459 Table 388 Endpoints assignment 463 Table 389 SETUP data memory status quadlet bit assignments 478 Table 390 Out data memory buffer status...

Page 42: ...gnments 530 Table 437 TTC field bit assignments 530 Table 438 RFD field bit assignments 531 Table 439 RFA field bit assignments 531 Table 440 RTC field bit assignments 532 Table 441 Interrupt enable r...

Page 43: ...ap 569 Table 490 Location of AC huffman codes in JPGCHuffEnc memory 569 Table 491 Location of DC huffman codes in JPGCHuffEnc memory 570 Table 492 Settings of K L and N 1 parameters for SIR MIR and FI...

Page 44: ...e 542 IC_CON register bit assignments 622 Table 543 IC_TAR register bit assignments 624 Table 544 IC_SAR register bit assignments 625 Table 545 IC_HS_MADDR register bit assignments 625 Table 546 IC_DA...

Page 45: ...Table 595 FSMC control and timing registers summary 666 Table 596 FSMC identification registers summary 667 Table 597 GenMemCtrl i register bit assignments 667 Table 598 GenMemCtrl_tim i register bit...

Page 46: ...RIRQSIGEN register bit assignments 723 Table 645 ACMD12ERSTS register bit assignments 723 Table 646 Relation between auto CMD12 CRC error and auto CMD12 timeout error 724 Table 647 CAP1 register bit a...

Page 47: ...ignments 761 Table 698 Telecom block pin signals 765 Table 699 I2S interface pins 777 Table 700 Camera interface signal 781 Table 701 Telecom address map 783 Table 702 Telecom registers 783 Table 703...

Page 48: ...em DRAM clocked by PLL1 817 Table 737 Power state for asynchronous DRAM system DRAM clocked by PLL2 818 Table 738 Techniques applicable in NORMAL state 820 Table 739 Modules supporting DCS technique 8...

Page 49: ...oller block diagram 287 Figure 24 System mode control state machine 290 Figure 25 SMI block diagram 299 Figure 26 External SPI memory map in AHB address space 301 Figure 27 Watchdog module block diagr...

Page 50: ...d issue sequence 686 Figure 73 Command completion sequence 687 Figure 74 Data transaction sequence without DMA 689 Figure 75 Data transaction sequence with SDMA 691 Figure 76 Data transaction sequence...

Page 51: ...9 Figure 107 Keyboard controller block diagram 810 Figure 108 Operative system control states 817 Figure 109 Clock supply 822 Figure 110 Typical power consumption with DDR2 333 MHz 823 Figure 111 Typi...

Page 52: ...l Bus BIST Built In Self Test BS Basic Subsystem CBC Cipher Block Chaining CTR Counter CMOS Complimentary Metal Oxide Semiconductor CRC Cyclic Redundancy Check DAC Digital to Analog Convertor DES Data...

Page 53: ...ubsystem RF Radio Frequency RFU Reserved for Future Use RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock RX Receive SDIO Secure Digital Input Output SHA 1 Secure Hash Al...

Page 54: ...base Examples d19 unsized decimal value 8 h2C 8 bit wide hexadecimal value of 0x2C corresponding to b00101100 8 b011001 8 bit wide binary value of b00011001 32 hFFFF 32 bit wide hexa decimal value of...

Page 55: ...1 55 844 3 Reference documentation 1 ARM926EJ S Technical reference manual 2 AMBA specification ARM IHI 0011A rev 2 0 3 USB 2 0 specification 4 OHCI specification 5 EHCI specification 6 ISO IEC 10918...

Page 56: ...ce overview An outline picture of the main SPEAr300 functional interfaces is shown in Figure 1 Figure 1 SPEAr300 top view SPEAr300 I2C SSP UART IrDA ADC Serial FlashInterface SMI GPIO DDR2 DDRLow Powe...

Page 57: ...data bus width supporting external asynchronous SRAM NAND NOR Flash 3 x SPI Master Slave Motorola Texas_National Master Slave up to 50 Mbps SDIO interface supporting SPI SD1 SD4 and SD8 mode with car...

Page 58: ...Operating frequency SW programmable Clock gating functionality Low frequency operating mode Automatic power saving controlled from application activity demands Architecture easily extensible External...

Page 59: ...t Mac USB 2 0 device JTAG ETM9 Reconfigurable Array Subsystem RAS USB 2 0 host 3 4 1 2 12 4 5 2 3 7 3 4 8 5 F L Reconfigurable A rray Subsystem CPU ARM subsystem ARM926EJS Coprocessor TCM I D GPIO Int...

Page 60: ...d to almost all the system blocks Low Speed Subsystem Application Subsystem Basic Subsystem High Speed Subsystem DDR Controller Port 2 RAS F RAS G RAS I and two DDR Controller Port 3 4 6 Dynamic memor...

Page 61: ...I and EHCI The PHYs are embedded One host controller at a time can perform high speed transfer One USB device compatible with USB 2 0 high speed specifications A dedicated channel connects the periphe...

Page 62: ...ing connection of NOR or NAND Flash and asynchronous SRAM Possible NAND Flash or parallel NOR Flash booting Color LCD Controller supports upto 1024 x 768 resolution 24 bpp true colour STN TFT display...

Page 63: ...erates the clock for the RAS block and for the DDR Memory interface Both the PLLs offer an EMI reduction mode Dithering than can replace all traditional drop methods for Electro Magnetic Interference...

Page 64: ...typical crystal in Oscillator 2 5 V capable MCLK_XO P2 Output 24 MHz typical crystal out RTC RTC_XI E2 Input 32 kHz crystal in Oscillator 1 5 V capable RTC_XO E1 Output 32 kHz crystal out Reset MRESE...

Page 65: ...1 5 V Table 5 Debug pin descriptions Group Signal name Ball Direction Function Pin type DEBUG TEST_0 K16 Input Test 4 0 configuration ports For functional mode they have to be set to 00110 TTL input b...

Page 66: ...Bidirectional analog buffer 5 V tolerant DEV_DM M2 USB Device D DEV_VBUS G3 Input USB Device VBUS TTL input buffer 3 3 V tolerant PD HOST1_DP H1 I O USB HOST1 D Bidirectional analog buffer 5 V toleran...

Page 67: ...up Signal name Ball Direction Function Pin type ADC AIN_0 N16 Input ADC analog input channel Analog buffer 2 5 V tolerant AIN_1 N15 AIN_2 P17 AIN_3 P16 AIN_4 P15 AIN_5 R17 AIN_6 R16 AIN_7 R15 ADC_VREF...

Page 68: ...U2 DDR_ADD_4 U3 DDR_ADD_5 U4 DDR_ADD_6 U5 DDR_ADD_7 T5 DDR_ADD_8 R5 DDR_ADD_9 P5 DDR_ADD_10 P6 DDR_ADD_11 R6 DDR_ADD_12 T6 DDR_ADD_13 U6 DDR_ADD_14 R7 DDR_BA_0 P7 Output Bank select DDR_BA_1 P8 DDR_B...

Page 69: ...DDR_GATE_0 R10 I O Lower Gate Open DDR_DATA_8 T17 I O Data Lines Upper byte DDR_DATA_9 T16 DDR_DATA_10 U17 DDR_DATA_11 U16 DDR_DATA_12 U14 DDR_DATA_13 U13 DDR_DATA_14 T13 DDR_DATA_15 R13 DDR_DQS_1 U1...

Page 70: ...buffer TTL 3 3 V tolerant selectable internal pull up pull down PU PD The PL_GPIOs can be configured in 13 different modes This allows SPEAr300 to be tailored for use in various applications see Secti...

Page 71: ...xers shown in Figure 3 are controlled by different registers The first multiplexer selects the I O functions of the RAS IPs in one of 13 modes shown in Configuration mode columns in Table 13 This sele...

Page 72: ...description RM0082 72 844 Doc ID 018672 Rev 1 Figure 3 Multiplexing scheme PL_GPIO Alternate functions RAS IP configuration mode 1 RAS Register 1 RAS Register 2 RAS IP configuration mode 13 16 bits 4...

Page 73: ...ed is Modes 5 7 8 and 9 up to 8 devices Modes 3 and 10 up to 6 devices Modes 11 and 12 up to 4 devices Modes FSMC Boot pins SPI I2C Multi slave control I2S CLCD DAC Camera interface TDM No of voice de...

Page 74: ...COL8 DIO3_1 DIO3_1 COL8 87 G13 D9 DQ9 D9 ROW0 ROW0 ROW0 ROW0 G8_1 G8_1 ROW0 ROW0 ROW0 ROW0 86 E17 D10 DQ10 D10 ROW1 ROW1 ROW1 ROW1 G8_2 G8_2 ROW1 ROW1 ROW1 ROW1 85 F15 D11 DQ11 D11 ROW2 ROW2 ROW2 ROW...

Page 75: ...A15 0 A18 CLD18 SPI_I2C6 CLD18 SPI_I2C6 CLD18 SPI_I2C6 SPI_I2C6 Reserved CLD18 Reserved CLD18 61 E12 0 A19 CLD19 SPI_I2C7 CLD19 SPI_I2C7 CLD19 SPI_I2C7 DOUT SPI_I2C7 DOUT Reserved CLD19 Reserved CLD19...

Page 76: ...CLK I2S_CLK I2S_CLK TDM_SYN C3 I2S_CLK I2S_CLK I2S_CLK I2S_CLK I2S_CLK 39 A9 UART_DCD H5 H5 GPIO0 I2S_ DOUT I2S_ DOUT I2S_ DOUT I2S_ DOUT TDM_SYN C2 DOUT I2S_DOUT I2S_DOUT I2S_DOUT I2S_DOUT 38 A8 UART...

Page 77: ...DIO10_1 DIO5 18 D5 MII_RX_ERR 0 0 G10_1 G10_1 G10_1 G10_1 G10_1 G10_1 G10_1 DIO4 DIO11_1 DIO11_1 DIO4 17 C4 MII_RXD0 0 0 G10_2 G10_2 G10_2 G10_2 G10_2 G10_2 G10_2 DIO3 DIO12_1 DIO12_1 DIO3 16 E6 MII_...

Page 78: ...TCLK TCLK CCLK TCLK CK2 J17 PL_CLK2 Reserved Reserved int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK int_CLK CK3 J16 PL_CLK3 Reserved Reserved int_CLK int_CLK int_CLK...

Page 79: ...ing Ex test instruction of JTAG Typically this configuration is used to verify correctness of the soldering process during the production flow 2 Case 2 All the PL_GPIO maintain their original meaning...

Page 80: ...tional I O ARM_TRACE_PKTB 1 PL_GPIO 90 BSR Value Functional I O ARM_TRACE_PKTB 2 PL_GPIO 89 BSR Value Functional I O ARM_TRACE_PKTB 3 PL_GPIO 88 BSR Value Functional I O ARM_TRACE_SYNCA PL_GPIO 87 BSR...

Page 81: ...escription Doc ID 018672 Rev 1 81 844 PL_GPIO 73 BSR Value Functional I O ARM_TRACE_PKTB 7 PL_GPIO 72 0 Table 15 Ball sharing during debug continued Signal Case 1 Board debug Case 2 Static debug Case...

Page 82: ...0 0xF7FF FFFF Table 17 Multi layer CPU subsystem 0xF800 0000 0xFFFF FFFF Table 19 Basic subsystem Table 17 Multi layer CPU subsystem Start address End address Peripheral Notes Bus 0xF000 0000 0xF00F F...

Page 83: ...om Boot ROM Table 20 High speed subsystem Start address End address Peripheral Notes Bus 0xE000 0000 0xE07F FFFF Reserved APB 0xE080 0000 0xE0FF FFFF Ethernet ctrl MAC AHB 0xE100 0000 0xE10F FFFF USB2...

Page 84: ...0x84000000 0x8400_0000 0x87FF_FFFF FSMC NAND on PCBank1 0x88000000 0x8800_0000 0x8BFF_FFFF FSMC NAND on PCBank2 0x8C000000 0x8C00_0000 0x8FFF_FFFF FSMC NAND on PCBank3 0x90000000 0x9000_0000 0x90FF_FF...

Page 85: ...th advanced operating system like Linux The ARM926EJ S supports the 32 bit ARM and 16 bit thumb instruction sets enabling the user to trade off between high performance and high code density and inclu...

Page 86: ...on accesses The Memory Management Unit MMU uses a single unified Translation Look aside Buffer TLB to cache the information held in the page tables To support both sections and pages there are two lev...

Page 87: ...KB Instruction Cache and 16 KB Data Cache The caches have the following features Virtual index virtual tag addressed using the Modified Virtual Address MVA Four way set associative with a cache line l...

Page 88: ...oth instruction and data access enabling multi layer AHB and multi AHB systems to be implemented giving the benefit of increased overall bus bandwidth and a more flexible system architecture To increa...

Page 89: ...ticular using a single FIQ source at a time in the system provides interrupt latency reduction because the ISR can be directly executed without determining the source of the interrupt Support for 16 v...

Page 90: ...15 and finally non vectored interrupts 8 3 2 Non vectored FIQ interrupt logic The non vectored FIQ interrupt logic block generates the FIQ interrupt signal by combining the FIQ interrupt requests com...

Page 91: ...interrupt block is associated to the 32 bit address of the ISR to be executed These ISR addresses are mapped in the VICVECTADDRi with i 0 15 registers Section 8 6 14 VICVECTADDR register The VICVECTAD...

Page 92: ...aphic Experts Group 16 Low Speed Subsystem IrDA Infrared Data Association 17 Low Speed Subsystem ADC Analog to Digital Converter 18 Low Speed Subsystem UART Universal Asynchronous Receiver and Transmi...

Page 93: ...e registers which can be accessed at the base addresses 0xF110_0000 VIC registers can be logically divided in four main groups Interrupt control and status registers listed in Table 25 for interrupt c...

Page 94: ...iption VICVECTADDR 0x030 RW 32 h0 Vector address VICDEFVECTADDR 0x034 RW 32 h0 Default vector address VICVECTADDR0 0x100 RW 32 h0 Vector address registers VICVECTADDR1 0x104 RW 32 h0 VICVECTADDR2 0x10...

Page 95: ...32 h0 Vector Control VICVECTCNTL1 0x204 RW 32 h0 VICVECTCNTL2 0x208 RW 32 h0 VICVECTCNTL3 0x20C RW 32 h0 VICVECTCNTL4 0x210 RW 32 h0 VICVECTCNTL5 0x214 RW 32 h0 VICVECTCNTL6 0x218 RW 32 h0 VICVECTCNT...

Page 96: ...LECT register The VICINTSELECT is a RW register which allows to select whether the corresponding interrupt generates an FIQ or an IRQ interrupt The VICINTSELECT bit assignments are given in Table 32 T...

Page 97: ...in Table 35 Table 32 VICINTSELECT register bit assignments Bit Name Reset value Description 31 00 IntSelect 32 h0 Each bit is associated to an interrupt line Each bit allows to select the type of inte...

Page 98: ...active interrupt The VICVECTADDR bit assignments are given in Table 38 Table 35 VICSOFTINT register bit assignments Bit Name Reset value Description 31 00 SoftInt 32 h0 Each bit is associated to a sou...

Page 99: ...ction 8 6 7 VICINTENABLE register and the interrupt is set to generate an IRQ interrupt in the VICINTSELECT register Section 8 6 6 VICINTSELECT register This prevents multiple interrupts being generat...

Page 100: ...set value Table 43 shows the bit assignments for this register Table 40 Peripheral identification registers bit assignments Bit Name Description 31 24 Configuration This is the configuration option of...

Page 101: ...ithin the register determine the reset value Table 45 shows the bit assignments for this register 8 6 23 VICPCELLID1 register The read only VICPCELLID1 register with address offset 0xFF4 is hard coded...

Page 102: ...gister 8 6 25 VICPCELLID3 register The read only VICPCELLID3 register with address offset 0xFFC is hard coded and the fields within the register determine the reset value Table 48 shows the bit assign...

Page 103: ...ion matrix Table 49 SoC interconnection matrix scheme Ethernet MAC C3 USB Host and Device RAS _E RAS L Processor DMA 1 DMA 2 RAS H Targets MemCtr 0 REQ MemCtr 1 REQ MemCtr 2 lcm5 REQ1 REQ2 MemCtr 3 lc...

Page 104: ...eir address and control signals stored into their input stage When address and control signals are stored into an input stage then the stored transfer controls the request and lock generation circuitr...

Page 105: ...cheme fixed priority or round robin Bit 30 28 specifies the priority starting level in case of round robin arbitration protocol Then 3 bit are allocated to each layer to set the priority level in case...

Page 106: ...layer PHY and some DLL that allows a fine tuning of all the timing parameter to maximize the data valid windows at every frequency in the allowed range Figure 7 MPMC block diagram 10 2 Signal descript...

Page 107: ...B CFG Through this bus connected to the multilayer interconnection matrix output port 3 the CPU or any other logic block with master capability can configure the memory controller registers AHB0 Throu...

Page 108: ...charge Read write grouping Bank splitting Bank grouping Swapping Aging Full initialization of memory on memory controller reset DRAM controller supports both DDR Mobile and DDR2 memory devices DDR Mo...

Page 109: ...a single read data interface back from the core controller to the port interface blocks The architecture of the multi port system is shown in Figure 8 Figure 8 Memory controller architecture The inter...

Page 110: ...relative to the main Memory Controller core clock These ports initialize in asynchronous operation but can be changed by programming the associated ahbY_fifo_type_reg parameter For more information on...

Page 111: ...WRITE data and READ data to the appropriate clock domain Port Core Pseudo Synchronous b01 The port frequency is twice the Memory Controller core frequency although the clocks are aligned in phase One...

Page 112: ...e Memory Controller core buffers Settings Reset There are two sets of reset logic inside the Memory Controller the reset for the Memory Controller core and the reset for the AHB ports The reset signal...

Page 113: ...complete set of AHB transactions The list includes SINGLE INCR4 INCR8 INCR16 WRAP4 WRAP8 WRAP16 and INCR For documentation purposes INCRx will refer to INCR4 INCR8 or INCR16 commands WRAPx will refer...

Page 114: ...o the data word boundary Clearing these parameters will cause the port to issue commands of 0 length to the Memory Controller core which the core interprets as the pre configured value of 1024 The val...

Page 115: ...the word in several bursts The reverse operation is done for INCRx READ transactions The AHB port issues a READ of the complete word and then divides the READ data into smaller components depending o...

Page 116: ...0x6 0x Aa BYTE 0x7 0xAa HALF WORD 0x0 0x BbAa HALF WORD 0x2 0x BbAa HALF WORD 0x4 0x BbAa HALF WORD 0x6 0xBbAa WORD 0x0 0x DdCcBbAa WORD 0x4 0xDdCcBbAa Table 57 READ WRITE data alignment Big Endian T...

Page 117: ...IZE AHBx Address INCR16 Byte half word or word AHBx Address 16 x AHBx HSIZE AHBx Address WRAP4 offset n 0 3 Byte half word or word Transaction 1 AHBx Address Transaction 2 Wrapped AHBx Address Transac...

Page 118: ...ment of the AHB protocol Error handling Once a port error is detected in the Memory Controller core the following actions occur 1 The internal interrupt signal controller_int is asserted 2 A bit in th...

Page 119: ...d queue there are also many factors that affect the actual latency of the command These factors include The coherency status of the transactions already in the command queue If there is a data coheren...

Page 120: ...atency are Read latency with a page hit and empty queue 9 Cas Latency Read latency with a page miss to a closed page and an empty queue Trcd Cas latency 9 Read latency with a page miss to an open page...

Page 121: ...tration scheme To understand the operation each concept must be first understood individually This will be matter of the following Sections 10 5 2 Understanding round robin operation Round robin opera...

Page 122: ...e can reach this level by aging 10 5 4 Understanding relative priority Inside each priority group the relative priority is used to set arbitration The Memory Controller contains 8 identical priority g...

Page 123: ...onding to the ratio of that port s relative priority ahbX_priorityY_relative_priority to the sum of all requesting port s relative priority values If a particular port is not requesting it will be not...

Page 124: ...for valid incoming transactions If there is an active request it will be accepted Otherwise the next port in the scan order will be checked For Memory Controller performing weighted round robin arbitr...

Page 125: ...nce let us consider the system described in Table 62 The counters refer to the ones inside each port priority group to guarantee that relative priorities are maintained To simplify on assumes the comm...

Page 126: ...s one only priority group is acting as shown in Table 63 Ports 4 and 5 can only win arbitration when no higher priority commands exist Table 63 System D operation Cycle Ports requesting Arbitration wi...

Page 127: ...t for this port to be processed This brings a random latency for each port but the maximum latency is fixed at the ahbX_priority_relax value If the current port does not have any commands waiting when...

Page 128: ...rtant to observe Cycles 1 and 7 A port relaxes while a higher priority request and a higher scan order request are both present The relaxed port still wins arbitration Cycle 4 Two ports of the same pr...

Page 129: ...for the sum calculation This means that the bandwidth will be divided differently among the ports Let us consider the port pair at the top of the scan order if one only port is requesting it will win...

Page 130: ...rt pair dynamically moves to the bottom of the scan order In Cycle 8 the port pair P4 P5 reaches its allocated relative priority However since these are the only requests at priority 1 the scan order...

Page 131: ...its 0 2 or 3 are set to 1 b1 in the wrr_param_value_err parameter and any of the ports are paired in the weighted_round_robin_weight_sharing parameter all weight sharing data will be ignored during Me...

Page 132: ...ssed inside Memory Controller is critical to proper system behavior While READs and WRITEs to different addresses are independent and may be re ordered without affecting system performance READs and W...

Page 133: ...portant commands from less important commands Each command is given a priority based on the command type through the programmable parameters ahbX_r_priority and ahbX_w_priority X is the x th port wher...

Page 134: ...ting at the top of the command queue while another command possibly of a lower priority is in process The high priority command swapping feature allows this new high priority command to be executed qu...

Page 135: ...devices 10 7 1 Low power modes Five low power modes are available in the Memory Controller The low power modes are listed from least to most power saving Note It is not possible to exit one low power...

Page 136: ...f except to a small portion of the DLL which must remain active to maintain the lock Before the memory devices are removed from self refresh the Memory Controller and memory clocks will be gated on 10...

Page 137: ...s programmed for manual entry by clearing the relevant bit in the lowpower_auto_enable parameter to 1 b0 The particular mode is set to 1 b1 in the lowpower_control parameter For manual entry the lowpo...

Page 138: ...f the associated bit in the lowpower_auto_enable parameter is set to 1 b1 the Memory Controller will watch the associated counter for expiration and then enter that low power mode Table 71 shows the c...

Page 139: ...ain the current frequency Since the voltage and temperature differences of the chip can change and the DLL would not adjust to these changes it is possible that the Memory Controller DLL shifts out of...

Page 140: ...emory Controller is able to support refresh operations to subsections of the memory array To simplify this duty separate parameters are provided to supply the EMRS data for each chip select These are...

Page 141: ...down resistors on the DRAM boundary to the DQS and DQS_n pins These resistors enable the system to open the gate early without receiving bad data Both the resistors are very important and the system c...

Page 142: ...le of latency If the bit is set to 1 b1 the standard path is used 10 9 Address mapping The Memory Controller automatically maps user addresses to the DRAM memory in a contiguous block Address map begi...

Page 143: ...ce sizes The settings for the addr_pins and column_size parameters control how the address map is used to decode the user address to the DRAM chip selects and row and column addresses The eight_bank_m...

Page 144: ...clock cycle Write transfer path are control from dqs_out_shift and wr_dqs_shift register parameters which set the delay for the DQS signal for dll_wr_dqs_slice and for the clk_wr signal respectively...

Page 145: ...at_lin parameter However to accommodate the skew of the memory devices it may be necessary to open the gate a 1 2 cycle sooner or later Adjusting the value of caslat_lin_gate modifies the gate opening...

Page 146: ...3020202 MEM68_CTL 0x001E007A MEM14_CTL 0x02040202 MEM69_CTL 0x00000000 MEM15_CTL 0x00000002 MEM70_CTL 0x00000000 MEM16_CTL 0x00000000 MEM71_CTL 0x00000000 MEM17_CTL 0x03000405 MEM72_CTL 0x00000000 MEM...

Page 147: ..._CTL 0x00200020 MEM105_CTL 0x00000000 MEM51_CTL 0x00200020 MEM106_CTL 0x00000000 MEM52_CTL 0x00000000 MEM107_CTL 0x00860000 MEM53_CTL 0x00000000 MEM108_CTL 0x00000002 MEM54_CTL 0x00000A24 Table 75 MT4...

Page 148: ...0x00000000 MEM28_CTL 0x01010102 MEM83_CTL 0x00000000 MEM29_CTL 0x01010101 MEM84_CTL 0x00000000 MEM30_CTL 0x00000001 MEM85_CTL 0x00000000 MEM31_CTL 0x00000000 MEM86_CTL 0x00000000 MEM32_CTL 0x00000000...

Page 149: ...ess refers to the register address reg_addr not a signal on the command address line The registers are not byte addressable unless the register width is defined as 8 bits To read or write a single par...

Page 150: ...P MEM3_CTL 0x0C 0x03 RW RD RW RW DLL_BYPASS_MODE DLLLOCKREG DDRII_SDRAM_MODE CONCURRENTAP MEM4_CTL 0x10 0x04 RW RW RW RW INTRPTAPBURST FAST_WRITE EIGHT_BANK_MODE DQS_N_EN MEM5_CTL 0x14 0x05 RW RW RW R...

Page 151: ...EM14_CTL 0x38 0x0E RW RW RW RW AHB4_R_PRIORITY AHB4_PORT_ORDERING AHB3_W_PRIORITY AHB3_R_PRIORITY MEM15_CTL 0x3C 0x0F RW AHB4_W_PRIORITY MEM16_CTL 0x40 0x10 This register intentionally blank MEM17_CTL...

Page 152: ..._RELATIVE_PRIORITY AHB2_PRIORITY3_RELATIVE_PRIORITY MEM26_CTL 0x68 0x1A RW RW RW RW AHB3_PRIORITY2_RELATIVE_PRIORITY AHB3_PRIORITY1_RELATIVE_PRIORITY AHB3_PRIORITY0_RELATIVE_PRIORITY AHB2_PRIORITY7_RE...

Page 153: ...x9C 0x27 RW RW DLL_DQS_DELAY_1 DLL_DQS_DELAY_0 MEM40_CTL 0xA0 0x28 RW DQS_OUT_SHIFT MEM41_CTL 0xA4 0x29 RW WR_DQS_SHIFT MEM42_CTL 0xA8 0x2A RW RW RW TRFC TRCD_INT TRAS_MIN MEM43_CTL 0xAC 0x2B RW RW AH...

Page 154: ...0x100 0x40 This register intentionally blank MEM65_CTL 0x104 0x41 RW DLL_DQS_DELAY_BYPASS_0 MEM66_CTL 0x108 0x42 RW RW DLL_INCREMENT DLL_DQS_DELAY_BYPASS_1 MEM67_CTL 0x10C 0x43 RW RD DLL_START_POINT...

Page 155: ...This register intentionally blank MEM91_CTL 0x16C 0x5B This register intentionally blank MEM92_CTL 0x170 0x5C This register intentionally blank MEM93_CTL 0x174 0x5D This register intentionally blank M...

Page 156: ...ad Only WR Write Only RW READ WRITE where one or more bits of the parameter have additional functionality and require special handling Table 77 Registers overview continued Register name Offset Mem CT...

Page 157: ...ller core 07 02 Reserved Read undefined Write should be zero 01 00 AHB3_FIFO_TYPE 0x0 0x0 0x1 Clock domain correlation between port 3 and Memory Controller core Table 80 MEM2_CTL register bit assignme...

Page 158: ...I mobile or DDRII 07 01 Reserved Read undefined Write should be zero 00 CONCURRENTAP 0x0 0x0 0x1 Allow controller to issue CMDs to other banks while a bank is in auto precharge Table 82 MEM4_CTL regis...

Page 159: ...rrupt a combined write CMD with auto pre charge with another write CMD 07 01 Reserved Read undefined Write should be zero 00 INTRPTREADA 0x0 0x0 0x1 Allow the controller to interrupt a combined read w...

Page 160: ...undefined Write should be zero 00 REG_DIMM_EN 0x0 0x0 0x1 Enable registered DIMM operation of the controller Table 86 MEM8_CTL register bit assignments Bit Name Reset value Range Description 31 25 Res...

Page 161: ...eserved Read undefined Write should be zero 09 80 MAX_CS 0x2 0x0 0x2 Maximum number of chip selects available READ ONLY 07 02 Reserved Read undefined Write should be zero 01 00 CS_MAP 0x0 0x0 0x3 Spec...

Page 162: ...om port 0 23 19 Reserved Read undefined Write should be zero 18 16 AHB0_PORT_ORDERING 0x0 0x0 0x7 Reassigned port order for port 0 15 11 Reserved Read undefined Write should be zero 10 08 ADDR_PINS 0x...

Page 163: ...9 Reserved Read undefined Write should be zero 18 16 AHB2_W_PRIORITY 0x0 0x0 0x7 Priority of write commands from port 2 15 11 Reserved Read undefined Write should be zero 10 08 AHB2_R_PRIORITY 0x0 0x0...

Page 164: ...00 AHB4_W_PRIORITY 0x0 0x0 0x7 Priority of write commands from port 4 Table 94 MEM16_CTL register bit assignments Bit Name Reset value Range Description 31 00 Reserved Read undefined Write should be...

Page 165: ...ved Read undefined Write should be zero 18 16 TRRD 0x0 0x0 0x7 DRAM TRRD parameter in cycles 15 03 Reserved Read undefined Write should be zero 02 00 TEMRS 0x0 0x0 0x7 DRAM TEMRS parameter in cycles T...

Page 166: ...MDs from port 0 07 06 Reserved Read undefined Write should be zero 05 00 AGE_COUNT 0x0 0x0 0x3F Initial value of master generate counter for CMD aging Table 99 MEM21_CTL register bit assignments Bit N...

Page 167: ...port 1 07 04 Reserved Read undefined Write should be zero 03 00 AHB0_PRIORITY7_RELATIVE_ PRIORITY 0x0 0x0 0xF Relative priority of priority 7 CMDs from port 0 Table 101 MEM23_CTL register bit assignme...

Page 168: ...port 2 07 04 Reserved Read undefined Write should be zero 03 00 AHB1_PRIORITY7_RE LATIVE_PRIORITY 0x0 0x0 0xF Relative priority of priority 7 CMDs from port 1 Table 103 MEM25_CTL register bit assignme...

Page 169: ...port 3 07 04 Reserved Read undefined Write should be zero 03 00 AHB2_PRIORITY7_RE LATIVE_PRIORITY 0x0 0x0 0xF Relative priority of priority 7 CMDs from port 2 Table 105 MEM27_CTL register bit assignm...

Page 170: ...port 4 07 04 Reserved Read undefined Write should be zero 03 00 AHB3_PRIORITY7_R ELATIVE_PRIORITY 0x0 0x0 0xF Relative priority of priority 7 CMDs from port 3 Table 107 MEM29_CTL register bit assignme...

Page 171: ...bit assignments Bit Name Reset value Range Description 31 00 Reserved Read undefined Write should be zero Table 110 MEM34_CTL register bit assignments Bit Name Reset value Range Description 31 28 Rese...

Page 172: ...e should be zero 05 00 COMMAND_AGE _COUNT 0x00 0x0 0x3F Initial value of individual CMD aging counters for CMD aging Table 112 MEM36_CTL register bit assignments Bit Name Reset value Range Description...

Page 173: ...Table 114 MEM38_CTL register bit assignments Bit Name Reset value Range Description 31 Reserved Read undefined Write should be zero 30 24 INT_STATUS 0x0 0x0 0x7F Status of interrupt features in the c...

Page 174: ...4 DQS_OUT_ SHIFT 0x0 0x0 0x7F Fraction of a cycle to delay the write dqs signal to the DRAMs during WRITEs 23 00 Reserved Read undefined Write should be zero Table 117 MEM41_CTL register bit assignmen...

Page 175: ...0 0x3FF Counter value to trigger priority relax on port 0 Table 120 MEM44_CTL register bit assignments Bit Name Reset value Range Description 31 26 Reserved Read undefined Write should be zero 25 16 A...

Page 176: ...t assignments Bit Name Reset value Range Description 31 26 Reserved Read undefined Write should be zero 25 16 AHB0_WRCNT 0x000 0x000 0x7FF Number of bytes for an INCR WRITE CMD on port 0 15 11 Reserve...

Page 177: ...ble 126 MEM50_CTL register bit assignments Bit Name Reset value Range Description 31 26 Reserved Read undefined Write should be zero 25 16 AHB3_WRCNT 0x000 0x000 0x7FF Number of bytes for an INCR WRIT...

Page 178: ...d be zero 13 00 TREF 0x0000 0x0000 0x3FFF DRAM TREF parameter in cycles Table 130 MEM55_CTL register bit assignments Bit Name Reset value Range Description 31 15 Reserved Read undefined Write should b...

Page 179: ...Bit Name Reset value Range Description 31 24 Reserved Read undefined Write should be zero 23 00 TINIT 0x000000 0x0 0xFFFFFF DRAM TINIT parameter in cycles Table 135 MEM60_CTL register bit assignments...

Page 180: ...ll_rd_dqs_slice 0 during READs when DLL is being bypassed 15 00 Reserved Read undefined Write should be zero Table 139 MEM66_CTL register bit assignments Bit Name Reset value Range Description 31 26 R...

Page 181: ...Reset value Range Description 31 26 Reserved Read undefined Write should be zero 25 16 wr_dqs_shft_byps 0x0 0x1 0x3FF Number of delay elements to include in the ddr_close signal in the controller when...

Page 182: ...ing as little endian or big endian 07 01 Reserved Read undefined Write should be zero 00 active_aging 0x0 0x0 0x1 Enable command aging in the command queue Table 145 MEM101_CTL register bit assignment...

Page 183: ...Write should be zero 09 08 lowpower_refresh_en able 0x0 0x0 0x3 Enable refreshes during power down 07 01 Reserved Read undefined Write should be zero 00 tref_enable 0x0 0x0 0x1 Issue self refresh CMDs...

Page 184: ...gating 15 00 lowpower_ext_cnt 0x0 0x0 0xFFFF Counts idle cycles to self refresh with memory clock gating Table 150 MEM106_CTL register bit assignments Bit Name Reset value Range Description 31 16 lowp...

Page 185: ...that the user address space is mapped contiguously into the memory map based on the value of this parameter For details please refer to Section 10 9 on page 142 age_count 5 0 Holds the initial value...

Page 186: ...ransmitted by the AHB port If the INCR command is terminated on an unnatural boundary the logic will discard the unnecessary words The value defined in this parameter should be a multiple of the numbe...

Page 187: ...parameter is dependent on the memory device since the same caslat value may have different meanings to different memories This will be programmed into the DRAM devices at initialization The CAS encodi...

Page 188: ...delay to include in the CKE signal cke_status for status reporting The default delay is 0 cycles column_size 2 0 Shows the difference between the maximum column width available 14 and the actual numbe...

Page 189: ...med into the delay parameters exceeds the number of delay elements in the delay chain the delay will be set to the maximum number of delay elements in the delay chain 1 b0 Normal operational mode 1 b1...

Page 190: ...of delay elements available 6 drive_dq_dqs 0 Selects whether the DQ output enables and DQS output enables will be driven active when the Memory Controller is in idle state 1 b0 Leave the output enabl...

Page 191: ...bits are set to b1 the corresponding bit in the int_status parameter will be set to b0 Any int_ack bits set to 1 b0 does not affect the corresponding bit in the int_status parameter This parameter wil...

Page 192: ...down mode Mode 1 For every bit 1 b0 Automatic entry into this mode is disabled The user may enter this mode manually by setting the associated lowpower_control bit 1this parameter is set to b1 Automat...

Page 193: ...un gated time will be longer Please refer to Section 10 7 on page 135 for more details lowpower_self_refresh_cnt 15 0 Counts the number of cycles to the next memory self refresh low power mode Please...

Page 194: ...ination Bit 0 If set to b1 CS0 will have active ODT termination when chip select X us performing a READ Bit 1 If set to b1 CS1 will have active ODT termination when chip select X is performing a READ...

Page 195: ...nt logic to fill the command queue 1 b0 Disabled 1 b1 Enabled pwrup_srefresh_exit 0 Controls controller to exit power down mode by executing a self refresh instead of the full memory initialization 1...

Page 196: ...d 2 b01 75 Ohm 2 b10 150 Ohm 2 b11 Reserved rw_same_en 0 Enables READ WRITE grouping as a condition when using the placement logic to fill the command queue 1 b0 Disabled 1 b1 Enabled srefresh 0 When...

Page 197: ...memories use this parameter If tDAL is defined in the memory specification then program this parameter to the specified value If the memory does not specify a tDAL time then this parameter should be...

Page 198: ...NR parameter in cycles txsr 15 0 Defines the DRAM self refresh exit time in cycles user_def_reg_0 31 0 Bit 31 1 Reserved Bit 0 Controls READ data retime 1 b0 Read data retime in circuit 1 b1 Read data...

Page 199: ...r can interrupt a WRITE burst with a READ command Some memory devices do not allow this functionality 1 b0 The device does not support READ commands interrupting WRITE commands 1 b1 The device does su...

Page 200: ...ction with the DDR2 mode enable bit ddrii_sdram_mode will cause an interrupt 8 Only one chip select and therefore 1 bit may be set at any time 9 Only one chip select and therefore 1 bit may be set at...

Page 201: ...ed the PLL output clock is modulated and the frequency assumes a triangular shape In this way the clock power spectrum is spread on a small range programmable of frequencies decreasing the emission po...

Page 202: ...ber of samples of the clock jitter are measured the values will usually hold to a normal distribution The interpretation of peak to peak jitter depends upon the effects of the jitter RTC PLL1 PLL2 PLL...

Page 203: ...sor clock Figure 14 Processor clock According to the state machine see Chapter 14 BS_System controller for full detail the CPU clock can be derived from the following sources External crystal 24 MHz P...

Page 204: ...rough the misc CORE_CLK_CFG PRPH_CLK_CFG register is possible to define the ratio between the CPU clock and its HCLK the ratio between the AHB and the APB clock and also the source for the peripheral...

Page 205: ...new clock with frequency DIV_CPT 16bit DIV15 0 M S bypass tck2 inv I2S_CLK Pin ClkR_Gpio4 0 ClkR_30MHz ClkR_Gpio4 ClkR Synt 2 Isrc2 0 SPEAR BISC CLOCK I2S M S Internal clock clock TDM int_clk TDM lin...

Page 206: ...output period is The output frequency is given by formula When Y X is not an integer value the output period swings between N and N 1 times the input clock period with N the integer part of Y X This m...

Page 207: ...l Connection Note The value of the capacitors depend on the type of the selected crystal As an example in STM reference board we have chosen RAKON P N Xtal003325 24 MHz oscillator the value of the cap...

Page 208: ...of miscellaneous registers 12 1 Signal description The next table shows the APB system interface Table 155 APB interface signals Miscellaneous Registers APB APB I F Control Reg n Reg 0 Reg 1 Status Co...

Page 209: ...ip The region controls Programmable logic RAS configuration Global command and status events Optional processor mail box data 12 3 Register address map Two different register address maps are provided...

Page 210: ...Platform basic configuration parameters Switch matrix arbitration protocol and priority definition DMA channel assignment scheme USB2 Pays setting parameter Special configuration parameters Compensat...

Page 211: ...x050 R W Reserved 0x054 Reserved 0x058 Reserved 0x05C IRDA_CLK_SYNT_CFG 0x060 R W UART0_CLK_SYNT_CFG 0x064 R W MAC_CLK_SYNT_CFG 0x068 R W RAS_CLK_SYNT1_CFG 0x06C R W RAS_CLK_SYNT2_CFG 0x070 R W RAS_CL...

Page 212: ...0 R W Reserved 0x0D8 Reserved 0x0DC POWERDOWN_CFG_CTR 0x0E0 R W COMPSSTL_1V8_CFG 0x0E4 R W Reserved 0x0E8 COMPCOR_3V3_CG 0x0EC R W DDR_PAD 0x0F0 R W BIST1_CFG_CTR 0x0F4 R W BIST2_CFG_CTR 0x0F8 R W BIS...

Page 213: ...AD_PRG 0x134 R W PLGPIO2_PAD_PRG 0x138 R W PLGPIO3_PAD_PRG 0x13C R W PLGPIO4_PAD_PRG 0x140 R W Reserved 32448 0x144 0x7FFC Table 157 Miscellaneous local space registers overview continued Misc Local S...

Page 214: ..._1 Same as Dyn_cfg0_0 but ARM JTAG connected with main JTAG interface X00010 Dyn_cfg0_2 Same as Dyn_cfg0_1 but ETM Interface Single and double packet mode multiplexed with programmable PL_GPIOs 73 97...

Page 215: ...JTAG interface X01110 Dyn_cfg3_2 Same as Dyn_cfg3_1 but ETM Interface Single and double packet mode multiplexed with programmable PL_GPIOs 73 97 SoC Test Configuration Type SoC Cfg Name Description X1...

Page 216: ...egister 0x004 Bit Name Reset Value Description 31 16 RFU Reserved for future use Write don t care Read return zeros 15 debug_freez 1 h0 Enable freeze condition when processor enters in debug mode 14 1...

Page 217: ...with main JTAG Interface 2 b01 Dyn_cfg0 1 2 3_2 ETM1 ARM ETM interface single double packets mode multiplexed with programmable PL_GPIO 38 14 signals ref ETM Dbg6 signal assessment tab JTAG1 connecte...

Page 218: ..._TRCPKTA 7 PL_GPIO 76 ARM1_TRCPKTB 4 PL_GPIO 75 ARM1_TRCPKTB 5 PL_GPIO 74 ARM1_TRCPKTB 6 PL_GPIO 73 ARM1_TRCPKTB 7 PL_GPIO 86 ARM1_PIPSTATA 0 PL_GPIO 85 ARM1_PIPSTATA 1 PL_GPIO 84 ARM1_PIPSTATA 2 PL_G...

Page 219: ...escription 31 09 RFU Reserved for future use Write don t care Read return zeros 08 03 pll_control1 6 h0 PLL Main Configuration Table Control Bit Description Pll_control1 8 1 b0 1 b1 External feedback...

Page 220: ...escription Table 161 PLL1 2_FRQ register bit assignments PLL1_FRQ Register PLL2_FRQ 0x00C 0x018 Bit Name Reset Value Description 31 16 pll_fbkdiv_M 16 h A600 M 15 0 PLL feedback divisor values when PL...

Page 221: ...1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 32 1 1 1 32 07 00 pll_prediv_N 8 h0C N 7 0 PLL pre divisor programmable value from 1 to 255 ref Pre divisor table The reference clock fref should be within the r...

Page 222: ...tion period mp as detailed in the next formula Example If fref 24000 kHz and fmod 100 kHz the modulation period register will be mp 60 Any changes in the reference clock results in changes in the modu...

Page 223: ...rence frequency is 2x HCLK DDR_CLK 2 x HCLK Note Ratio 2 1 must also be be set in the ahbX_fifo_type_reg parameter see Table 151 in Section 11 3 b010 Reserved for future use 3 b011 Asynch mode core cl...

Page 224: ...lock this field reflects the current value of System PLL2 lock signal RO 1 b0 PLL2 unlock status for interrupt capability ref SYSERR_CFG_CTR register description 1 b1 Pll2 active lock This field shoul...

Page 225: ...ription Table 164 CORE_CLK_CFG register bit assignments CORE_CLK_CFG Register 0x024 Bit Name Reset Value Description 31 22 RFU Reserved for future use Write don t care Read return zeros 21 20 Osci24_d...

Page 226: ...ow speed subsystem PCLK clock ratio divider ref next table HCLK to PCLK clock ratio configuration table Control bit Ratio Description 2 b00 1 1 Hclk to Pclk clock ratio 2 b01 1 2 Hclk to Pclk clock ra...

Page 227: ...CLK_CFG n 11 gptmr2_clksel 1 h0 GPT2 General purpose timer 2 source clock selection 1 b0 48 MHz default clock 1 b1 Clock prescaler PRSC2_CLK_CFG 10 09 RFU Reserved for future use Write don t care Read...

Page 228: ...les an auxiliary timer to control the switch transition from doze to slow operating mode when system controller Xtal timeout event expires 1 b0 Disable Xtal timer functionality the switch transition i...

Page 229: ...Disable ROM controller clock 1 b1 Enable ROM controller clock 19 DMA_clkenb 1 h0 1 b0 Disable DMA controller clock 1 b1 Enable DMA controller clock 18 GPIO_clkenb 1 h0 1 b0 Disable GPIO clock 1 b1 Ena...

Page 230: ...nb 1 h0 ARM clock enable functionality asserted setting 0 the PERIPH1_CLK_ENB 1 after a previous write with PERIPH1_CLK_ENB 1 0 01 1 b0 Disable ARM clock gating functionality 1 b1 Enable ARM clock gat...

Page 231: ...nal synthesizer 1 source clock 1 b1 Enable internal synthesizer 1 source clock 07 pll2_clkenb 1 h0 1 b0 Disable PLL2 source clock 1 b1 Enable PLL2 source clock 06 RFU 05 clk48M_clkenb 1 h0 1 b0 Disabl...

Page 232: ...urn zeros 15 12 presc_n 4 h0 N 3 0 constant factor division value N 16 11 00 presc_m 12 h0 M 11 0 constant division value M 4096 Table 169 AMEM_CFG_CTRL register bit assignments AMEM_CFG_CTRL Register...

Page 233: ...efinition ref next table Memory port2 source clock configuration table Control Bit Description 3 b000 HCLK synchronous operating mode 3 b001 PLL1 clock synthesizer should be enable 3 b010 PLL2 clock s...

Page 234: ...K_SYNT1_CFG RAS_CLK_SYNT2_CFG RAS_CLK_SYNT3_CFG RAS_CLK_SYNT4_CFG 0x054 to 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 Bit Name Reset Value Description 31 synt_clk_enb 1 h0 Enable clock synthesize...

Page 235: ...b1 Active USB ehci host reset 25 usbh1_ohci_s wrst 1 h1 1 b0 Disable USB ohci host reset 1 b1 Active USB ohci host reset 24 usbdev_swrst 1 h1 1 b0 Disable USB device reset 1 b1 Active USB device rese...

Page 236: ...JPEG codec reset 07 i2c_swrst 1 h1 1 b0 Disable I2 C reset 1 b1 Active I2 C reset 06 RFU Reserved for future use 05 ssp_swrst 1 h1 1 b0 Disable SPI reset 1 b1 Active SPI reset 04 RFU 1 h1 Reserved fo...

Page 237: ...ras_synt3_swr st 1 h1 1 b0 Disable reset command 1 b1 Active reset command 09 ras_synt2_swr st 1 h1 1 b0 Disable reset command 1 b1 Active reset command 08 ras_synt1_swr st 1 h1 1 b0 Disable reset com...

Page 238: ...igh speed subsystem ICM 5 2 Memory controller port 2 ICM 6 2 RAS_F port ICM 7 4 Memory controller port 3 ICM 8 2 Memory controller port 4 Table 175 ICM 1 9_ARB_CFG register bit assignments ICM1_ARB_CF...

Page 239: ...pry_lyr 3 3 h0 Master layer 3 fixed priority number level from 0 to 7 This field is relevant only for ICM7_ARB_CFG registers ref Fixed priority number level definition table 08 06 mtx_fix_pry_lyr 2 3...

Page 240: ...in The register bit assignment is given in the next table 02 00 mtx_fix_pry_lyr 0 3 h0 Master layer 0 fixed priority number level from 0 to 7 ref next table Fixed priority level definition table Contr...

Page 241: ...n version CHAN Sch_0 00 Sch_1 01 31 30 dma_cfg_chan 15 2 h0 15 FROM_JPEG RAS_7 Tx 29 28 dma_cfg_chan 14 2 h0 14 TO_JPEG RAS_7 Rx 27 26 dma_cfg_chan 13 2 h0 13 ADC RAS_6 Tx 25 24 dma_cfg_chan 12 2 h0 1...

Page 242: ...This bit controls the state of PLL blocks when in Suspend mode 1 b0 PLL blocks powered up during Suspend mode 1 b1 PLL blocks powered down during Suspend mode Table 178 MAC_CFG_CTR register bit assig...

Page 243: ...I Txclk Rxclk 25 2 5 MHz Table 178 MAC_CFG_CTR register bit assignments continued MAC_CFG_CTR Register 0x0A8 Bit Name Reset Value Description Table 179 Powerdown_CFG_CTR register bit assignments Power...

Page 244: ...during Read operating mode command ref Compensation cell operating mode table 23 RFU Reserved for future use Write don t care Read return zeros 22 16 nasrc Read code compensation parameter RO this fie...

Page 245: ...care Read return zeros 04 COMPOK 1 h0 Valid code compensation RO field actives high in normal mode when the measured code is available on the compensation bus nasrc 03 ACCURATE 1 h0 Compensation cell...

Page 246: ...connected to PDCLK of SSTL differential pads 08 DQS_PU_sel 1 h0 DQS pull up it is connected to PUCLK of SSTL different pads 07 CLK_PDN_sel 1 h1 Programmable CLK Pull down functionality connected with...

Page 247: ...of the pad 02 PROG_a 1 h0 Combination of these bits selects the speed of operation of PAD 00 200 MHz 01 266 MHz 10 333 MHz 11 Prohibited 01 PROG_b 1 h1 00 DDR_LOW_POWER_ DDR2_mode 1 h0 It selects DDR...

Page 248: ...ble Memory Bist Command Table Bist command Peripherals Tm Ret Rbacktx Iddq Debug 0 0 1 0 0 Run BIST 0 0 0 0 1 Scan collar 0 1 0 0 0 Read 0 retention test 0 1 0 0 1 Read 1 retention test 0 0 0 1 0 Iddq...

Page 249: ...command table Rbact Memory cut Peripherals 14 ST_DPHS_2048X32m8_Lb Low speed shrd men 13 ST_DPHD_96X128m4_b HWACC Application subssystem HWACC 12 ST_SPREG_384X12m4_L JPEG HUFFENC 11 ST_SPREG_416X8m4_...

Page 250: ...Read return zeros 28 bist2_rst 1 h0 Reset BIST engine collar 1 b0 Disable reset 1 b1 Active reset 27 26 25 24 bist2_tm bist2_debug bist2_ret bist2_iddq 1 h0 1 h0 1 h0 1 h0 Memory BIST interface comma...

Page 251: ...e use Write don t care Read return zeros 28 bist3_rst 1 h0 Reset BIST engine collar 1 b0 Disable reset 1 b1 Active reset 27 26 25 24 bist3_tm bist3_debug bist3_ret bist3_iddq 1 h0 1 h0 1 h0 1 h0 Memor...

Page 252: ...ive reset 30 29 RFU Reserved for future use Write don t care Read return zeros 28 bist4_rst 1 h0 Reset BIST engine collar 1 b0 Disable reset 1 b1 Active reset 27 26 25 24 bist4_tm bist4_debug bist4_re...

Page 253: ...b0 BIST execution ok 1 b1 BIST execution fails ref next table Run BIST status table Rbact Memory cut Peripherals 14 ST_DPHS_2048X3 2m8_Lb Low speed shrd mem 13 ST_DPHD_96X128 m4_b HWACC Application su...

Page 254: ...emory sub group The register bit assignments is given in the next table Table 188 BIST2_STS_RES register bit assignments BIST2_STS_RES Register 0x10C Bit Name Reset Value Description 31 bist2_end End...

Page 255: ...m8_Lb Ras buf Sp8Kx8_1 12 ST_DPHS_1024x 32m8_Lb Ras buf Sp4Kx8_4 11 ST_DPHS_1024x 32m8_Lb Ras buf Sp4Kx8_3 10 ST_DPHS_1024x 32m8_Lb Ras buf Dp4Kx8_2 09 ST_DPHS_1024x 32m8_Lb Ras buf Dp4Kx8_1 08 ST_DPH...

Page 256: ...ion fails ref next table Bist failure table Bbad Memory Cut Peripherals 13 ST_SPHDL_2048 x8m16 Ras buf Sp2Kx8_8 12 ST_SPHDL_2048 x8m16 Ras buf Sp2Kx8_7 11 ST_SPHDL_2048 x8m16 Ras buf Sp2Kx8_6 10 ST_SP...

Page 257: ...rnal memory pool The register bit assignments is given in the next table Table 190 BIST4_STS_RES register bit assignments BIST4_STS_RES Register 0x114 Bit Name Reset Value Description 31 bist4_end End...

Page 258: ...12 ARM_SPREG_1024x3 2m8_b Arm ddata Sp1Kx32_3 11 ARM_SPREG_1024x3 2m8_b Arm ddata Sp1Kx32_2 10 ARM_SPREG_1024x3 2m8_b Arm ddata Sp1Kx32_1 09 ARM_SPREG_256x88 m2_b Arm dtag Sp256Kx22 08 ARM_SPREG_32x24...

Page 259: ...a Sp1Kx32_3 18 SPUHD1024x32m8_b Arm ddata Sp1Kx32_2 17 SPUHD1024x32m8_b Arm ddata Sp1Kx32_1 16 SPUHD1024x32m8_b Arm ddata Sp1Kx32_0 15 SP_64KUHD_256x22m4 Arm dtag Sp256Kx22_3 14 SP_64KUHD_256x22m4 Arm...

Page 260: ...g 1 b1 Memory transfer error asserted from memory controller when one of the following error event is active A single access outside the defined PHYSICAL memory space Multiple accesses outside the def...

Page 261: ...detection 07 RFU 06 wdg_err_enb 1 h0 Enable Watch dog timeout error interrupt detection 1 b0 Disable error detection 1 b1 Enable error detection 05 RFU Reserved for future use Write don t care Read re...

Page 262: ...nanoPHY s silicon characterization will determine whether any of these bits require a different setting other than the default 12 4 42 PLGPIOn_PAD_PRG Registers These five registers are used to progra...

Page 263: ...l up control for UART Pads 2 3 29 PDN_5 1 h1 Pull down control for pads 20 21 22 23 28 PUP_5 1 h0 Pull up control for pads 20 21 22 23 27 26 DRV_5 1 0 2 h0 Drive strength control for pads 20 21 22 23...

Page 264: ...ads 44 45 46 47 24 PDN_10 1 h0 Pull down control for pads 40 41 42 43 44 23 PUP_10 1 h1 Pull up control for pads 40 41 42 43 44 22 21 DRV_10 1 0 2 h0 Drive strength control for pads 40 41 42 43 20 SLE...

Page 265: ...r pads 64 65 66 67 22 21 DRV_16 0 2 h0 Drive strength control for pads 64 65 66 67 20 SLEW_16 1 h0 Slew control for pads 64 65 66 67 19 PDN_15 1 h1 Pull down control for pads 60 61 62 63 18 PUP_15 1 h...

Page 266: ..._21 1 h1 Pull down control for pads 84 85 86 87 18 PUP_21 1 h0 Pull up control for pads 84 85 86 87 17 16 DRV_21 1 0 2 h0 Drive strength control for pads 84 85 86 87 15 SLEW_21 1 h0 Slew control for p...

Page 267: ...RV_CLK4 1 0 2 h0 Drive strength control for pads CLK4 20 SLEW_CLK4 1 h0 Slew control for pads CLK4 19 PDN_CLK3 1 h1 Pull down control for pads CLK3 18 PUP_CLK3 1 h0 Pull up control for pads CLK3 17 16...

Page 268: ...8 0000 Register Name Alias 1 Offset 0x0 8000 Alias 2 Offset 0x1 8000 Type Register Displacement single region RAS_GPP1_IN 0x00 R W RAS_GPP2_IN 0x04 R W RAS_GPP1_OUT 0x08 R W RAS_GPP2_OUT 0x0C R W RAS_...

Page 269: ...ut register direct controls the programmable logic GPP_OUT 31 00 signals 1 b0 Force the corresponding bit signal low 1 b1 Force the corresponding bit signal high General purpose output command field T...

Page 270: ...le Separate transmit and receive first in first out memory buffers 16 bits wide 8 locations deep Programmable choice of interface operation SPI Microwire or TI synchronous serial Programmable data fra...

Page 271: ...ceive FIFO service request interrupt RORINTR Output 1 Receive overrun interrupt RTINTR Output 1 Receive timeout interrupt INTR Output 1 SSP interrupt This interrupt is an OR of the four individual int...

Page 272: ...llel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master respectively through the SSPTXD pin 13 4 5 Receive FIFO The common receive FIFO...

Page 273: ...set of sources from one wide register in the system interrupt controller This is attractive where the time to read from the peripheral registers is significant compared to the CPU clock speed in a re...

Page 274: ...it SSPTXD and receive SSPRXD pins Clock ratios There is a constraint on the ratio of the frequencies of PCLK to SSPCLK The frequency of SSPCLK must be less than or equal to that of PCLK This ensures t...

Page 275: ...x 256 x FSSPCLKOUT min for master mode FSSPCLK max 254 x 256 x FSSPCLKIN min for slave mode 13 5 3 Programming the SSPCR0 control register The SSPCR0 register is used to Program the serial clock rate...

Page 276: ...utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period For Motorola SPI and National Semiconductor Microwire frame formats the s...

Page 277: ...SPDR 0x008 R W 16 Receive FIFO read and transmit FIFO write data register SSPSR 0x00C RO 5 5 h3 Status register SSPCPSR 0x010 R W 8 8 h0 Clock prescale register SSPIMSC 0x014 R W 4 4 h0 Interrupt mask...

Page 278: ...5 08 SCR R W Serial clock rate The value SCR is used to generate the transmit and receive bit rate of the SSP The bit rate is PCLK CPSDVR 1 SPR Where CPSDVSR is an even value from 2 to 254 programmed...

Page 279: ...is eight bits the most significant byte is ignored The receive data size is controlled by the programmer The transmit FIFO and the receive FIFO are not cleared even when SSE is set to zero This allow...

Page 280: ...215 SSPDR register bit assignments Bit Name Type Description 15 00 DATA R W Transmit receive FIFO Read Receive FIFO Write Transmit FIFO You must right justify data when the SSP is programmed for a dat...

Page 281: ...st be an even number from 2 to 254 depending on the frequency of SSPCLK The least significant bit always returns zero on reads Table 218 SSPIMSC register bit assignments Bit Name Type Description 15 0...

Page 282: ...state prior to masking of the SSPRXINTR interrupt 01 RTRIS RO Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt 00 RORRIS RO Gives the raw interrupt state prior to masking of...

Page 283: ...gister bit assignments Bit Name Type Description 31 08 Reserved read as zero 07 00 PartNumber0 RO These bits read back as 0x22 Table 224 PHERIPHID1 register bit assignment Bit Name Type Description 31...

Page 284: ...can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSPIMSC register Setting the appropriate mask bit HIGH enables the interrupt Table 227 PCELLID0 register...

Page 285: ...ly the SSP and interrupts can be enabled so that data can be written to the transmit FIFO by an interrupt service routine 13 7 3 SSPRORINTR The receive overrun interrupt SSPORINTR is asserted when the...

Page 286: ...em Controller which is used to supply an interface to control the operation of the overall system Main features of the System Controller are listed below Provides a system mode control state machine I...

Page 287: ...MEEN PERIPHCLKSTAT 31 0 REDCLK TIMCLK WDEN SYSSTAT 31 0 REMAPSTAT nIRQ STANDBYWFI nFIQ SYSID 31 0 SCANENABLE SCANINSCLK PLLTIMEEN XTALON XTALSW Clock and reset inputs PLL oscillator control and status...

Page 288: ...register SLEEP mode During this mode the system clocks HCLK and CLK are disabled and the System Controller clock SCLK is driven from a low speed oscillator nominally 32 768 Hz When either a FIQ or an...

Page 289: ...clock source from the crystal oscillator to the low speed oscillator The system moves into the DOZE mode when the XTALSW input is set to PLL control transition state PLL CTL The PLL control transition...

Page 290: ...control of the crystal and PLL by using the crystal control register SCXTALCTRL Section 14 4 7 and the PLL control register SCPLLCTRL PLL frequency control To define the frequency of the clock generat...

Page 291: ...system controller provides access to the HCLKDIVSEL 2 0 output through the system control register namely the 3 bit field HCLKDivSel of the SCCTRL register Section 14 4 3 These output signals are int...

Page 292: ...address space Table 231 offset addresses from 0xF00 to 0xFDC are reserved for test purposes All these locations must not be used during normal operation Table 231 System controller control and status...

Page 293: ...nts Bit Name Reset value Description 31 24 Reserved Read undefined Write should be zero 23 WDogEnOv 1 h0 Watchdog enable override This bit allows to control the watchdog enable output signal Section 1...

Page 294: ...7 Reserved Read undefined Write should be zero 06 03 ModeStatus 4 h01 Mode status bitsThis 4 bit field returns the current operation mode as defined by the system controller state machine Section 14 3...

Page 295: ...should be zero 07 InMdType 1 h0 Interrupt mode type This bit is used to define which type of interrupt can cause the system to enter interrupt mode according to the encoding 1 b0 FIQ 1 b1 FIQ and IRQ...

Page 296: ...cycles permitted for the crystal oscillator output to settle after being enabled The timeout is given by 65536 XtalTime 02 XtalStat RO 1 h0 Crystal status bit This RO bit returns the value on the XTAL...

Page 297: ...he PLLEN output when the PLL control override is enabled PllOver bit set to b1 in this register 00 PllOver RW 1 h0 PLL control override If set this bit enables the PLL control signals from the system...

Page 298: ...M95040 M95020 and M95010 ATMEL AT25Fxx YMC Y25Fxx SST SST25LFxx Acts always as a SPI master and up to 2 SPI slave memory devices are supported through as many chip select signals with up to 16 MB add...

Page 299: ...ng as an AHB slave interface the SMI is accessed by AHB master through AHB bus The following rules apply to this interface Endianness is fixed to little endian SPLIT RETRY responses from AHB slave tha...

Page 300: ...device the related SPI slave must be selected by SMI through chip select then a 1 byte instruction must be sent by SMI to the selected memory The set of instructions supported by SMI is given in Table...

Page 301: ...ransfer any data or commands from transmit register SMI_TR Section 15 8 6 to external serial memory and to read data directly in the receive register SMI_RR Section 15 8 7 The transfer actually starts...

Page 302: ...5 5 2 Write request A write request from AHB master to external SPI memory is served only if SMI is in Hardware mode otherwise an error flag is set ERF1 flag in the SMI_SR register Section 15 8 5 Wrap...

Page 303: ...ode that is clearing the WBM bit in SMI_CR1 register the next incrementing AHB write request should be sent to external memory if it occurs before the end of the previous serial transfer Otherwise an...

Page 304: ...SMI clock frequency fSMI_CK fSMI_CK fAHB PRESC value that is tSMI_CK tAHB PRESC value being tSMI_CK and tAHB the clock period of the SMI clock and the AHB bus respectively Note If PRESC is an even val...

Page 305: ...al memory The device allows an external boot from a serial Flash only located at bank0 which is enabled after power on reset During the boot phase the following instructions sequence is automatically...

Page 306: ...MI The SMI_CR1 bit assignments are given in Table 241 Table 239 External pin connection Signal Ball SMI_DATAIN M13 SMI_DATAOUT M14 SMI_CLK N17 SMI_CS_0 M15 SMI_CS_1 M16 Table 240 SMI registers summary...

Page 307: ...lock frequency up to 50 MHz is available otherwise bit cleared it is reduced to 20 MHz 14 08 PRESC 7 h0 RW Prescaler value This 7 bit field allows to set the prescaler value used to generate the SMI_C...

Page 308: ...ast write enable read status register and send commands are not sent if the bank is disabled without any error message Table 241 SMI_CR1 register bit assignments continued Bit Name Reset value Type De...

Page 309: ...n 15 8 5 08 TFIE 1 h0 RW Transfer finished interrupt enable Setting this bit it allows to enable the issue of an interrupt request when software transfer complete event occurs This event also results...

Page 310: ...ifically if set ERF1 marks forbidden access to memory that is read write access requested on disabled bank read write access requested in software mode or read requests in write burst mode bit WBM set...

Page 311: ...ents are given in Table 245 08 TFF 1 h0 RO Transfer finished flag This bit is set when transfer with external memory is completed that is after REC_LENGTH and TRA_LENGTH bytes set in SMI_CR2 register...

Page 312: ...sfer is finished bit TFF set in SMI_SR register Table 243 otherwise the register content is not valid Note The SMI_RR is also used in Hardware mode but its content is not kept entering in this mode Ta...

Page 313: ...n on time out Reset signal generation on time out if the interrupt from the previous time out remains unserviced by software Lock register to protect registers from being altered by runaway software I...

Page 314: ...module registers through APB bus The external WDOGCLK signal which in conjunction with its clock enable WGDOGCLKEN is used to clock the Watchdog module counter and its associated interrupt and reset...

Page 315: ...Offset Type Reset value Description WdogLoad 0x00 RW 32 hFFFFFFFF Load register WdogValue 0x04 RO 32 hFFFFFFFF Value register WdogControl 0x08 RW 32 h0 Control register WdogIntClr 0x0C WO Interrupt c...

Page 316: ...to the WO WdogIntClr interrupt clear register clears the watchdog module interrupt Then the counter is re loaded with the value in the WdogLoad register and another count down sequence starts Table 24...

Page 317: ...ed Read undefined 00 WDOGRIS 1 h0 If set it indicates that an interrupt has been raised by the Watchdog counter reaching zero Table 251 WdogMIS register bit assignments Bit Name Reset value Descriptio...

Page 318: ...rent modes of operation are available setting the MODE bit in TIMER_CONTROL register Section 17 2 4 Auto reload mode an interrupt source is activated the counter is automatically cleared and then it r...

Page 319: ...nt of timing is done Used only in CAPTURE MODE TMR_CP TR2 B11 0xFCB0_0000 TMR_CL K3 B10 Output signal which toggles TIMER generates an interrupt OUTPUT generated for both TIMER CAPTURE MODE TMR_CL K4...

Page 320: ...GPT all internal registers are cleared when this input is driven low PADDR 8 2 In APB Bridge Standard APB address bus PSEL In APB Bridge Standard APB psel signal PENABLE In APB Bridge Standard APB pen...

Page 321: ...ister of 2nd timer in the couple GPT1 or GPT3 TIMER_STATUS_INT_ACK2 0x0104 RW 16 h0000 Status register of 2nd timer TIMER_COMPARE2 0x0108 RW 16 hFFFF Compare register of 2nd timer TIMER_COUNT2 0x010C...

Page 322: ...cleared Clearing this bit the GPT is disabled and capture as well as counter registers are frozen After reset the GPT is disabled and all interrupt sources are masked 04 MODE 1 h0 Operation mode This...

Page 323: ...er reaches the COMPARE_VALUE it is cleared and restarts TIMER_PERIOD COMPARE_VALUE 1 x COUNTER_PERIOD 2 TIMER_CLOCK periods 2 COUNTER_PERIOD is the period of the timer s input clock i e the prescaler...

Page 324: ...T register The TIMER_FEDG_CAPT timer falling edge capture is a RO register which is used to store the current value of the counter when a falling edge occurs When a capture has occurred the FEDGE bit...

Page 325: ...on any number of pins Bit masking in both read and write operation through address lines 18 2 Functional description 18 2 1 Block diagram Figure 29 shows the block diagram of GPIO Figure 29 GPIO block...

Page 326: ...l interrupt generation for details and actual input signals features a GPIO interrupt signal GPIOINTR is generated by the Interrupt Detection Logic block as the OR combination of all the GPIO masked i...

Page 327: ...ss bus is used according to the following rules During a write operation to GPIODATA register a data bit of the GPIODATA register is altered only if the associated address bit in PADDR 9 2 is set othe...

Page 328: ...ming model 18 5 1 Register map The GPIO can be fully configured by programming its 6 bit wide registers which can be accessed through the APB slave interface at the base address 0xFC98_0000 GPIO regis...

Page 329: ...isters summary Name Offset Type Width bit Reset Value Description GPIOIS 0x404 RW 6 6 h0 Interrupt Sense GPIOIBE 0x408 RW 6 6 h0 Interrupt Both Edges GPIOIEV 0x40C RW 6 6 h0 Interrupt Event GPIOIE 0x4...

Page 330: ...h have been configured as output through the GPIODIR register 18 5 5 GPIOIS register The GPIOIS Interrupt Sense is a RW register which allows configuring each pin to detect either a level or an edge f...

Page 331: ...iven in Table 273 Table 271 GPIOIBE register bit assignments Bit Name Reset value Description 05 00 GPIOIBE 6 h0 Each bit is associated to a pin If a bit is set both edges on the relevant pin trigger...

Page 332: ...bit assignments are given in Table 276 Table 274 GPIORIS register bit assignments Bit Name Reset value Description 05 00 GPIORIS 6 h0 Each bit is associated to a pin If a bit is set it indicates that...

Page 333: ...a single DMA request or a Burst DMA request with programmable size to increase data transfer effectiveness Hardware priority 0 the highest to 7 the lowest for each DMA channel to manage requests from...

Page 334: ...ces is given in Figure 33 Figure 33 DMAC signal interface diagram DMA REQUEST AND RESPONSE BLOCK AHB SLAVE INTERFACE CHANNEL 0 CHANNEL 1 CHANNEL 7 A R B I T E R A R B I T E R AHB MAST I F AHB MAST I F...

Page 335: ...it retry and error responses from AHB slaves If a peripheral performs a split or retry the DMAC stalls and waits until the transaction can complete Locked transfers for source and destination of each...

Page 336: ...emory Memory to peripheral Peripheral to memory Peripheral to peripheral where each transfer can have either the peripheral or the DMAC as the flow controller resulting then in eight different scenari...

Page 337: ...C allows to generate an interrupt to the ARM processor In case of a DMA error assertion of an error response on the AHB during data transfer At the end of DMA transfer terminal count reached 0 The cor...

Page 338: ...is set an error occurred step 6 6 Set the relevant bit in the DMACIntTCClear register Section 19 7 5 or in the DMACIntErrClr register Section 19 7 7 respectively to clear the interrupt request 19 7 Pr...

Page 339: ...hannel destination address DMACCnLLI 0x108 n 0x020 RW 32 h0 Channel linked list item DMACCnControl 0x10C n 0x020 RW 32 h0 Channel control DMACCnConfiguration 0x110 n 0x020 RW 32 h0 Channel configurati...

Page 340: ...is enough to determine source of the interrupt request 19 7 5 DMACIntTCClear register The DMACIntTCClear interrupt terminal count clear is a WO register which allow to clear a terminal count interrup...

Page 341: ...h00 Terminal count request clear Each bit is associated to a DMA channel When writing to this register each bit that is set causes the corresponding bit in the DMACIntTCStatus register to be cleared I...

Page 342: ...are given in Table 289 Table 287 DMACRawIntTCStatus register bit assignments Bit Name Reset value Description 31 08 Reserved Read undefined 07 00 RawIntTCStatus 8 h00 Status of the terminal count int...

Page 343: ...rst request is a RW register which enables DMA last burst requests to be generated by software The DMACSoftLBReq bit assignments are given in Table 292 Table 290 DMACSoftBReq register bit assignments...

Page 344: ...6 peripheral DMA request lines Setting a bit a DMA last burst request for the corresponding peripheral is generated and the bit is cleared when the transaction has completed Reading this field of the...

Page 345: ...d this register is updated As the source address is incremented By following the linked list when a complete packet of data has been transferred Reading the register when the DMA channel is active doe...

Page 346: ...case it shows the source address of the last item read 19 7 19 DMACCnLLI register The DMACCnLLI channel n linked list item is a RW register which contains the address word aligned of the next Linked L...

Page 347: ...ntrols whether the current LLI is expected to trigger the terminal count interrupt 30 28 Port 3 h0 Protection This 3 bits field reports AHB access information which are primarily intended to be used b...

Page 348: ...hen required Note Transfers wider than the AHB master bus width are illegal Besides the source and the destinations widths can be different from each other 17 15 DBSize 3 h0 Destination burst size Thi...

Page 349: ...he flow controller This value counts down from the original value to zero and a read from this field provides then the number of transfers still to be completed on the destination bus Note This field...

Page 350: ...y memory to peripheral according to encoding 3 b000 Memory to memory DMAC 3 b001 Memory to peripheral DMAC 3 b010 Peripheral to memory DMAC 3 b011 Source periph to destination periph DMAC 3 b100 Sourc...

Page 351: ...is ignored in case the destination resp source of the transfer is the memory Note The DestPeripheral and SrcPeripheral fields are the binary value of the request line 4 h0 to 4 hF that is 0 to 15 and...

Page 352: ...ogramming its 32 bit wide registers listed in Table 301 which can be accessed at the base address 0xFC90_0000 Table 301 RTC functional registers summary 20 2 2 Register description 20 2 3 CONTROL regi...

Page 353: ...o 05 00 MASK Force time calendar comparisons Each bit of this 6 bit field allows to mask one time calendar element seconds minutes hours days months years according to encoding The aim is to generate...

Page 354: ...ed only when this bit is cleared 02 PT RO Pending write to TIME register If set this bit indicates that a write to TIME register request is asserted from 48 MHz part to 32 kHz part A new write can be...

Page 355: ...in this ALARM TIME register are in binary coded decimal BCD format Table 305 DATE register bit assignments Bit Name Reset value Description 31 28 YM Current year millenniums 27 24 YH Current year hund...

Page 356: ...suspend to ram During this state only the DDR memory is powered and all the other parts of the system SOC included are completely off The REGxMC registers bit assignments are given in Table 308 and Ta...

Page 357: ...FFFF_1000 High performance DMA based co processor enabling the acceleration of data driven computationally expensive functions such as Cryptography Pattern matching Signal Processing etc Highly progra...

Page 358: ...Empty Channel 7 Empty Number of Instruction Dispatchers is 4 The configuration is as follows ID0 Available ID1 Empty ID2 Empty ID3 Empty Number Coupling Chaining Module internal cross bar for inter ch...

Page 359: ...hits an end of program instruction in which case it can signal the end of processing by the means of an interrupt request if programmed to do so C3 has two interfaces AHB Master Interface it is used t...

Page 360: ...ontains the instruction dispatchers up to 4 that are in charge of fetching the programs from memory and dispatch the instructions to the requested channels Since the instruction dispatchers operate in...

Page 361: ...can be directly received from sent to other channels without going through memory Support for multiple algorithms in the Core block The Core block implementation is application specific 21 4 5 CCM Co...

Page 362: ...channel executes the instruction The channel generally performs DMA access request for reading input data and parameters from system memory but it may be set up to receive data from another channel T...

Page 363: ...0 C3_CH2 Channel 2 Registers 0x2800 32 h400 C3_CH3 Channel 3 Registers 0x2C00 32 h400 unused 0x3000 32 h400 unused 0x3400 32 h400 unused 0x3800 32 h400 unused 0x3C00 32 h400 unused 0x4000 32 h400 unus...

Page 364: ...SCR Status and control register RW 0x000 SYS_STR Channel status register RO 0x040 SYS_VER Hardware version and revision RO VER 0x3F0 SYS_HWID Hardware ID RO HWID 0x3FC Bit 31 30 29 28 27 26 25 24 Symb...

Page 365: ...represents the state of the Interrupt pin of the C3 document Writing one to this flag has the same effect as writing one in all ISD3 ISDO Bit 18 Clear interrupt status on read CISR If the Clear Inter...

Page 366: ...Channels Channels 8 to 15 you must use the Channel Status Register SYS_STR Status and control register SYS_SCR Bit 16 ARST Description 1 b1 Reset the whole C3 1 b0 Clearing conditions This bit is cle...

Page 367: ...egister SYS_VER contain the RTL source version from which the Hardware was generated Hi Bit CnSH LoBit CnSL Description 0 0 Not Present This Channel does not exist in Hardware 1 0 Idle The Channel is...

Page 368: ...ts data access collisions from occurring ID0 has the highest priority to perform accesses on this block followed in order by ID1 to ID3 and Channels 0 to 15 lowest priority Read Transfers have higher...

Page 369: ...n asynchronous master reset The other way to access the internal Memory contents is making transfers to the C3 AHB Slave Interface There are two different methods to achieve this mapping a 512 Bytes p...

Page 370: ...ternal Memory in Bytes If an internal Memory does not exist in Hardware this register will be zero This is a way for the Software to know if an internal Memory is there and what its size is The maximu...

Page 371: ...ure for the Software to enable the Internal Memory is to first program its base address using HIF_MBAR and then enable it by setting the EMM bit of HIF_MCR The Internal Memory can be enabled or disabl...

Page 372: ...l res res res res res res DAIR DAIW Initial Value 0 0 Type R W R W Bit 15 14 13 12 11 10 9 8 Symbol res res res res res res res res Initial Value Type Bit 7 6 5 4 3 2 1 0 Symbol res res res res res re...

Page 373: ...Description 1 b0 Disable the Internal Memory Transactions from Channels and Instruction Dispatchers go either to the Bus or the Byte Bucket if enabled AHB slave accesses to the Internal Memory are not...

Page 374: ...this Bits B31 B16 read only are those programmed in the Internal Memory Base Address Register HIF_MBAR Bits 1 0 are always zero since only aligned 32 bit transactions are supported Initial Value 0 0 0...

Page 375: ...and Instruction Dispatcher write transactions that fall within a window of 64 KB starting from NBAR are then discarded by the Byte Bucket if enabled The Byte Bucket Base Address can be changed at any...

Page 376: ...the behaviour of the active transactions done in this range is undefined Bit 31 to 1 Reserved These bits are reserved and should be set to zero Bit 0 Enable Byte Bucket Mapping ENM Bit 31 30 29 28 27...

Page 377: ...ID_IR0 Instruction Word 0 Register RO 32 h0 0x020 ID_IR1 Instruction Word 1 Register RO 32 h0 0x024 ID_IR2 Instruction Word 2 Register RO 32 h0 0x028 ID_IR3 Instruction Word 3 Register RO 32 h0 0x02C...

Page 378: ...erved These bits are reserved and should be set to zero Bit 26 Channel Error CERR Channels report their states to each Instruction Dispatcher When the ID dispatches an instruction to a Channel that is...

Page 379: ...The Channel to which the current instruction was addressed is busy It is already running under control of another Instruction Dispatcher 1 b0 Cleaning Conditions This flag is cleared in three ways re...

Page 380: ...ispatcher generates an Interrupt on normal termination of a program execution when the stop instruction executes 1 b0 Do not generate Interrupt Cleaning this bit does not clear pending interrupts Bit...

Page 381: ...ion Pointer Register ID_IP The Instruction Pointer Register is used to store the pointer of the first instruction to be fetched and to launch program execution It can be read back at any time particul...

Page 382: ...resent reading zero from this register or using the ID_SCR or the SYS_SCR The Channel ID has no bit field structure the value is a mere index in a database table The database containing all the assign...

Page 383: ...that will go in error state 21 8 3 DES instructions There are 2 different DES instructions DES START DES APPEND The first instruction is used for setting the operation parameters such as the key and...

Page 384: ...struction is 3 words long This instruction is used to set the key and the initialization vector for the following operations The length of the key is encoded in the first instruction word the second w...

Page 385: ...st instruction word the second word represents the Source Address and the third word represents the Destination Address Bit a in the above table is used to set the algorithm to use Bit b in the above...

Page 386: ...ite operation The Data Output Registers contain the current data output of the DES Channel accessed using the read operation Note A read operation on these registers just after a write operation will...

Page 387: ...o Bit 2 Encryption Decryption ED This bit indicates the operation to perform Encryption or Decryption Bit 1 Mode of operation MODE This bit indicates the mode of operation ECB or CBC Bit 31 30 29 28 2...

Page 388: ...ecuting C3 Flow type instruction set 21 9 2 Instruction set The AES Channel executes AES START APPEND ENCRYPT and AES START APPEND DECRYPT instructions specified in the C3v3 flow type instruction set...

Page 389: ...to set the key and the initialization vector for the following operations The length of the key is encoded in the first instruction word the second word represents the Source Address for the key and...

Page 390: ...ECB The AES APPEND ECB instruction is 3 words long This instruction is used for passing the data to process encrypt or decrypt The length of the data to process is encoded in the first instruction wo...

Page 391: ...represents the Source Address and the third word represents the Destination Address Address Bit a in the above table is used to set the operation to perform and has the same encoding as in the ECB in...

Page 392: ...ion it depends on the selected mode AES_DATA_INOUT2 Data Input output register 2 R W 32 h0 0x008 AES_DATA_INOUT3 Data Input output register 3 R W 32 h0 0x00C AES_FEEDBACK0 Feedback register 0 R W 32 h...

Page 393: ...30 to 29 Key Size KEYSZ These 2 bits represent the key length as in the following internal representation For writing this field the bit 3 of the input word has to be set to 1 Bit 31 30 29 28 27 26 25...

Page 394: ...Bits 24 to 23 Context Save Restore CTX_SR These 2 bits represent the operation to do with the context as in the following internal representation For writing this field the bit 0 of the input word has...

Page 395: ...HMAC MD5 SHA1 instruction It can save and restore the internal context in order to allow the stop and the resume of the computation executing C3 Flow type instruction set s HASH CONTEXT and HMAC CONT...

Page 396: ...bove table are used to set the algorithm to use and have the same encoding as in the INIT instruction Table 333 Bits 15 to 0 in the first instruction word cccc in Table 334 represent the Count in Byte...

Page 397: ...on Address for the context 21 11 10 RESTORE The HASH CONTEXT RESTORE instruction is 2 words long This instruction is used to set the Source Address Register for the context and to restore the full con...

Page 398: ...oding as in the HASH INIT instruction Table 333 Bits 15 to 0 in the first instruction word cccc in Table 338 represent the length in Bytes of the key 21 11 14 APPEND The HMAC MD5 SHA1 APPEND instructi...

Page 399: ...rd represents the Source Address for the key while the third word represents the Destination Address for the HMAC Bits aa in the above table are used to set the algorithm to use and have the same enco...

Page 400: ...dress for the context Table 343 UHH channel registers map Symbol Name Type Initial value Address UHH_SR 1 Core Status Register R W 32 h0 0x020 UHH_HX0 1 Hash Status Register 0 R W 32 h0 0x024 UHH_HX1...

Page 401: ...0A0 UHH_UHR 1 Current Hash Constant R W 32 h0 0x0A4 UHH_BCLO 1 Bit Count Register LSW R W 32 h0 0x0A8 UHH_BCHI 1 Bit Count Register MSW R W 32 h0 0x0AC UHH_RK0 Digest of the HMAC key 0 R W 32 h0 0x0B0...

Page 402: ...32 h8000_000 0 0x200 CTAG_IR Channel ID RO 32 h0000_400 1 0x3FC 1 Marked registers compose the Context for saving and restoring in the same order as they are listed in table The context is composed b...

Page 403: ...ase the UHH Channel goes in error state and this bit is set Example the ID has dispatched the first word of the Hash Append instruction The UHH Channel is still waiting for the second word If the ID g...

Page 404: ...aborting instruction execution and bits 31 30 CS of UHH_CU_CONTROL_STATUS are set to Idle Bit 27 BERR Description 1 b1 The Channel was requested to become a Chaining master or simultaneously both a Co...

Page 405: ...e Last Word N BLW These 5 bits represent the length in bits of the last word of the message Bits 25 to 22 Cryptoblock Internal Status STAT These 4 bits represent the status of the Cryptoblock as in th...

Page 406: ...O_RESET_SHORT_KEY Init for HMAC with short key 4 b0101 HMAC_DO_RESET_LONG_KEY Init for HMAC with long key 4 b0110 HMAC_REQUEST_IKEY_SHORT Get the short inner key for HMAC 4 b0111 HMAC_REQUEST_IKEY_LON...

Page 407: ...2 b11 Not Used Bit 31 30 29 28 27 26 25 24 Symbol ALG1 ALG0 res res Res CPHA1 CPHA0 PST2 Initial Value 0 0 0 0 0 Type R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Symbol PST1 PST0 WCNT3 WCNT2 WCNT1...

Page 408: ...ash core Bits 17 to 14 HMAC State ST These bits represent the action in progress in the HMAC procedure Bit 31 to 30 Algorithm 2 b00 MD5 2 b01 SHA 1 2 b10 Not Used 2 b11 Not Used Bit 24 to 22 Algorithm...

Page 409: ...1 Last Word Asserted LAST This bit indicates if the whole message has been passed to the core 4 b0110 Pad short outer key 4 b0111 Wait for the HMAC 4 b1000 HMAC value is ready 4 b1001 Get long inner...

Page 410: ...message Current Hash Constant Register UHH_UHR The Current Hash Register contains the current result of the internal Hash function Bit Count Registers UHH_BCLO UHH_BCHI The Bit Count Registers contain...

Page 411: ...the commands for the UTMI PHY The UHC complies with both the Enhanced Host Controller Interface EHCI specification version 1 0 and the Open Host Controller Interface OHCI specification version 1 0a Th...

Page 412: ...for both EHCI and OHCI host controller registers access The AHB BIU Master module acting as a master on the AHB receives requests from the List Processor block Section 22 4 1 List processor within the...

Page 413: ...l the other EHCI Host Controller blocks such as the AHB BIU Master module the Packet Buffer the EHCI Operational registers the SOF Generators and the Root Hub 22 4 2 Operational registers This block e...

Page 414: ...ers with no breaks then a buffer overrun occurs In this case to avoid buffer overrun or under run PBUF size could be set to 1024 bytes 22 4 5 Root hub The Root Hub RH block interfaces between the List...

Page 415: ...the odd boundary not the DWORD boundary it reads only the lower 2 bit of the address ties them to 0 so that the application always writes at DWORD boundary and manipulates the byte enables accordingly...

Page 416: ...ital PLL runs on a 48 MHz user provided clock to extract the clock information from the USB for both Full Speed and Low speed data The two signals D and D of the USB lines are passed through a differe...

Page 417: ...following conditions are occurred Interrupt on Async Address Host System Error Frame List Rollover Port Change USB Error USB Interrupt But this interrupt is generated only when corresponding bits are...

Page 418: ...munication through one of the two ports by setting the corresponding PORTSC register in the EHCI Operation Register block The registers of the EHCI host controller can be grouped in four different cla...

Page 419: ...h0000A010 Capability parameters Table 347 EHCI host controller operational registers summary Name Offset 1 1 Offset calculated by reading HCCAPBASE The offset is kept with respect to the operational...

Page 420: ...8 12 RW 12 h080 Programmable packet buffer depth INSNREG03 USBOPBASE 0x8C 1 RW 1 h0 Break memory transfer INSNREG04 USBOPBASE 0x90 3 RW 3 h0 For debug purposes only INSNREG05 USBOPBASE 0x94 32 RW 32 h...

Page 421: ...Register name Table 351 HCCAPBASE register bit assignments Bit Name Reset value Description 31 16 HCIVERSION 16 h0100 This field contains a BCD encoding of the EHCI revision number supported by this h...

Page 422: ...OHCI host controller It is used to indicate the port routing configuration to system software The default convention bit PRR set to 0b0 is that the first N_PCC ports are assumed to be routed to compa...

Page 423: ...ream ports implemented on this EHCI host controller The value of this field ranging from 4 h1 to 4 hF that is 1 to 15 determines how many port registers are addressable in the auxiliary power well reg...

Page 424: ...the asynchronous schedule The park feature can be disabled or enabled as well as set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode count...

Page 425: ...12 Reserved Read undefined Write should be zero 11 ASPME 1 h1 Asynchronous schedule park mode enable This bit is used by software to enable bit set to 1 b1 or disable 1 b0 the Park mode If the asynchr...

Page 426: ...a 1 b1 to this bit to ring the doorbell When the EHCI host controller has evicted all appropriate cached schedule state it sets the interrupt on async advance status bit IAA bit 5 in the USBSTS regist...

Page 427: ...anion OHCI host controller s with the side effects This bit is cleared by the EHCI host controller when the reset process is complete Note Software cannot terminate the reset process early by writing...

Page 428: ...he USBCMD register When this bit and the asynchronous schedule enable bit are the same value the asynchronous schedule is either enabled or disabled 14 PSS 1 h0 Periodic schedule status The bit report...

Page 429: ...rom its maximum value to 0 The exact value at which the rollover occurs depends on the frame list size For example if the frame list size as programmed in the Frame list size FLS field of the USBCMD r...

Page 430: ...t of a TD that had its IOC bit set The EHCI host controller also sets this bit when a short packet is detected actual number of bytes received was less than the expected number of bytes 1 See EHCI doc...

Page 431: ...mes or micro frames before moving to the next index The actual number of bits that is N used for the frame list current index depends on the size of the frame list as set by system software in the FLS...

Page 432: ...gment is a RW register which corresponds to the most significant address bits 63 32 for all EHCI data structures If the 64 bit addressing capability 64BAC field in HCCPARAMS register is set to 1 b0 th...

Page 433: ...4 0 of this register cannot be modified by system software and will always return a zero when read 3 The memory structure referenced by this physical memory pointer is assumed to be 32 bytes cache li...

Page 434: ...ntroller Table 362 PORTSC register bit assignments Bit Name Reset value Description 31 23 Reserved Read undefined Write should be zero 22 WKOC_E 1 h0 Wake on over current enable Setting this bit enabl...

Page 435: ...to this bit when the attached device is not an HS device meaning that a companion OHCI host controller owns and controls the relevant port 12 PP 1 h0 Port Power The function of this bit depends on the...

Page 436: ...defined in the Universal Serial Bus Specification Revision 2 0 is started Software must keep this bit at a 1 b1 long enough to ensure the reset sequence completes Note When software writes this PR bit...

Page 437: ...1 In the suspend state the port is sensitive to resume detection Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a t...

Page 438: ...he appropriate amount of time has elapsed Writing a zero from one causes the port to return to high speed mode forcing the bus below the port into a high speed idle This bit will remain a one until th...

Page 439: ...not change until the port state actually changes There may be a delay in disabling or enabling a port due to other EHCI host controller and bus events This field is zero if port power PP bit in this r...

Page 440: ...registers The Host Controller HC contains a set of on chip operational registers which are mapped into a noncacheable portion of the system addressable space These registers are used by the Host Cont...

Page 441: ...6 24 The control and status partition 22 6 25 HcRevision register 22 6 26 HcControl register The HcControl register defines the operating modes for the Host Controller Most of the fields in this regi...

Page 442: ...01b USBRESUME 10b USBOPERATIONAL 11b USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later HCD may determine whether HC has begun sending SOFs by read...

Page 443: ...f isochronous EDs While processing the periodic list in a Frame HC checks the status of this bit when it finds an Isochronous ED F 1 If set enabled HC continues processing the EDs If cleared disabled...

Page 444: ...ingOverrun in HcInterruptStatus has already been set This is used by HCD to monitor any persistent scheduling problems 15 04 Reserved 03 OCR 00b R W R R OwnershipChangeRequest This bit is set by an OS...

Page 445: ...processing the Control list If CF is 1 HC will start processing the Control list and will set ControlListFilled to 0 If HC finds a TD on the list then HC will set ControlListFilled to 1 causing the Co...

Page 446: ...should not proceed with any processing nor signaling before the system error has been corrected HCD clears this bit after HC has been reset 03 RD 0b R W R W ResumeDetected This bit is set when HC dete...

Page 447: ...he HcInterruptStatus register The HcInterruptDisable register is coupled with the Table 370 HcInterruptEnable register bit assignments Bits Name Reset Read Write Description HCD HC 31 MIE 0b R W R A 0...

Page 448: ...found in Chapter 4 This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver Bits Name Reset Read Write Des...

Page 449: ...372 HcHCCA register bit assignments Bits Name Reset Read Write Description HCD HC 31 08 HCCA 0h R W R This is the base address of the Host Controller Communication Area 07 00 Reserved Bits Name Reset...

Page 450: ...ED This pointer is advanced to the next ED after serving the present one HC will continue processing the list from where it left off in the last Frame When it reaches the end of the Control list HC ch...

Page 451: ...e Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset Bits Name Reset Read Write Description HCD HC 31 04 BCED 0h R W R W BulkCurrentED This...

Page 452: ...n two consecutive SOFs in bit times The nominal value is set to be 11 999 HCD should store the current value of this field before resetting HC By setting the HostControllerReset field of HcCommandStat...

Page 453: ...r nor the Host Controller Driver are allowed to change this value Bits Name Reset Read Write Description HCD HC 31 16 Reserved 15 00 FN 0h R R W FrameNumber This is incremented when HcFmRemaining is r...

Page 454: ...tus and HcRhPortStatus 1 NDP Each register is read and written as a Dword These registers are only written during initialization to correspond with the system implementation The HcRhDescriptorA and Hc...

Page 455: ...otection supported 11 OCPM IS R W R OverCurrentProtectionMode This bit describes how the overcurrent status for the Root Hub ports are reported At reset this fields should reflect the same mode as Pow...

Page 456: ...cleared 0 all ports are powered at the same time 1 each port is powered individually This mode allows port power to be controlled by either the global switch or perport switching If the PortPowerContr...

Page 457: ...device is configured to global switching mode PowerSwitchingMode 0 this field is not valid bit 0 Reserved bit 1 Ganged power mask on Port 1 bit 2 Ganged power mask on Port 2 bit15 Ganged power mask on...

Page 458: ...ontrolMask bit is not set Writing a 0 has no effect 15 DRWE 0b R W R read DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume event causing a USBSUSPEND to USBRESUME state...

Page 459: ...ychronization delay The HCD writes a 1 to clear this bit Writing a 0 has no effect This bit is also cleared when ResetStatusChange is set 0 resume is not completed 1 resume completed 17 PESC 0b R W R...

Page 460: ...r SetGlobalPower HCD clears this bit by writing ClearPortPower or ClearGlobalPower Which power control switches are enabled is determined by PowerSwitchingMode and PortPortControlMask NDP In global sw...

Page 461: ...on this port This bit always reflects the overcurrent input signal 0 no overcurrent condition 1 overcurrent condition detected write ClearSuspendStatus The HCD writes a 1 to initiate a resume Writing...

Page 462: ...hange is set 0 port is disabled 1 port is enabled write SetPortEnable The HCD sets PortEnableStatus by writing a 1 Writing a 0 has no effect If CurrentConnectStatus is cleared this write does not set...

Page 463: ...ected to the AHB bus and generates the commands for the UTMI PHY Hereafter the UDC along with AHB interface is referred to UDC AHB subsystem The UDC AHB supports the 480 Mbps high speed HS for USB 2 0...

Page 464: ...am USB 1 1 Transceiver External RAM IN Endpoints READ Port WRITE Port EP FIFO CNTRL 1 EP FIFO CNTRL 2 EP FIFO CNTRL N External RAM OUT Endpoints READ Port WRITE Port Control Status Registers SOF Track...

Page 465: ...hem to the receive FIFO Section 23 3 4 Receive FIFO controller Besides for data transmission to an USB Host that is an in transaction the UTLI reads data to be transmitted from relevant endpoint FIFO...

Page 466: ...frame counter operated by the SOF tracker itself to the 11 bit frame number provided by the UDC Note In order to provide backward compatibility with the FS 1 ms frame of USB 1 1 in HS mode the frame...

Page 467: ...status register Endpoint status register on page 499 to determine the number of bytes to be transferred before to start the appropriate AHB transfers with an appropriate HSIZE i e 32 16 or 8 Note Any...

Page 468: ...w to exchange control information with the application as well as provide a means for the application to control the UDC AHB Subsystem 23 3 7 AHB slave only interface The AHB slave only interface bloc...

Page 469: ...imultaneously although transmit and receive functions cannot be performed simultaneously From a functional perspective the DMA controller parses the descriptor structures and then commands the other s...

Page 470: ...timal use of system memory which is indeed a major design constraint on portable systems Specifically in DMA mode the UDC AHB subsystem implements a true scatter gather memory distribution in which me...

Page 471: ...ed this endpoint then the application probes the endpoint status register Endpoint status register on page 499 to determine the interrupt s cause Upon notification that this is an in token for a parti...

Page 472: ...for isochronous endpoints with a frame number The UDC which maintains the frame counter sends the isochronous data in the intended frame whereas the SOF tracker module SOF tracker on page 466 tracks t...

Page 473: ...register on page 503 Out data is transferred to the buffers indicated by the descriptor and the pointer for these descriptors is programmed in the CSRs Note The SETUP data directly addresses the buffe...

Page 474: ...slave only implementation the application acts as an AHB master to read data from or to write data to the memory mapped subsystem FIFOs and the UDC AHB subsystem operates as a AHB slave for both data...

Page 475: ...e interrupt s cause Once the application determines that an in token for the endpoint requested the interrupt it writes the packet directly to the address where the associated TxFIFO is mapped As soon...

Page 476: ...etried SETUP out packets are stored in a temporary subsystem register before being loaded to the receive FIFO Once the packet is transferred to the RxFIFO the subsystem sends an interrupt to the appli...

Page 477: ...sfer is described by the following example flow At first write the initial data PID bit 17 16 in the endpoint buffer size in register Endpoint buffer size and received packet frame number register on...

Page 478: ...b10 DMA done Buffer data transfer completed by DMA 2 b11 Host busy The application is processing the descriptor 29 28 Rx Sts Receive status This 2 bit field reports the status of the received SETUP da...

Page 479: ...memory structure is given in Figure 47 Table 390 reports the bits assignments for out buffer status quadlet If the buffer status of the first descriptor is set to host ready see BS field in Table 390...

Page 480: ...bit field reports the status of the received out data according to encoding reflecting whether the out data has been correctly received or some errors occurred 2 b00 Success 2 b01 DESERR descriptor t...

Page 481: ...b10 DMA done Buffer data transfer completed by DMA 2 b11 Host busy The application is processing the descriptor 29 28 Rx Sts Receive status This 2 bit field reports the status of the received out data...

Page 482: ...ncoding reflecting whether the in data has been correctly transmitted or some errors occurred 2 b00 Success 2 b01 DESERR descriptor transfer error 2 b10 Reserved 2 b11 BUFFER data transfer error 27 L...

Page 483: ...in which the current iso out packet is transmitted This 11 bit field gives the frame number in which the current iso in packet is transmitted according to the following bits assignments 26 19 Millisec...

Page 484: ...simultaneously sends an interrupt to the application 23 6 3 Buffer fill mode IN In case of in transactions the DMA buffer fill mode can be entered by using the packet per buffer mode with only one de...

Page 485: ...sed by the UPD block when the USB host is attached detached This interrupt is putted in OR with the output of the Interrupt Manager block and the output of he OR logic goes to the VIC block Two 32 bit...

Page 486: ...Tri state the USB 2 0 PHY is in non driving mode 02 phy_rst 1 h1 USB PHY reset If set this bit indicates that the USB PHY is in reset mode otherwise it is in normal mode 01 state 1 h0 USB host connect...

Page 487: ...xE100_0800 Offset addresses from 0x0800 up to a 0x1800 host the data in the RxFIFO Receive FIFO controller on page 466 which are followed by the memory space allocated to TxFIFOs Table 396 In endpoint...

Page 488: ...point 0 Reserved 0x02A0 0x02BC 6 As Endpoint 0 0x02C0 0x02DC As Endpoint 0 Reserved 0x02E0 0x02FC 8 As Endpoint 0 0x0300 0x031C As Endpoint 0 Reserved 0x0320 0x033C 10 As Endpoint 0 0x0340 0x035C As E...

Page 489: ...register 0x0514 RW 32 h0 5 UDC20 Endpoint register 0x0518 RW 32 h0 6 UDC20 Endpoint register 0x051C RW 32 h0 7 UDC20 Endpoint register 0x0520 RW 32 h0 8 UDC20 Endpoint register 0x0524 RW 32 h0 9 UDC2...

Page 490: ...t value Description 31 19 Reserved Read undefined Write should be zero 18 SET_DESC 1 h0 Set descriptor requests support This bit states how the USB device replies to set Descriptor request according t...

Page 491: ...mes in FS operation which depends on the PHY s delay in generating a line state condition The default timeout value is 16 bit times 09 PHY_ERRO R DETECT 1 h0 PHY error detection Setting this bit the U...

Page 492: ...n Table 401 Device control register bit assignments Bit Name Reset value Description 31 24 THLEN 1 8 h00 Threshold length This 8 bit field indicates the number THLEN 1 of 32 bit entries in the RxFIFO...

Page 493: ...Burst split enable on page 485 is enabled and burst length is programmed by the BRLEN field in this register 07 THE 1 1 h0 Thresholding enable Setting this bit the DMA threshold Threshold enable on p...

Page 494: ...ported in DMA mode only Table 401 Device control register bit assignments continued Bit Name Reset value Description Table 402 Device status register bit assignments Bit Name Reset value Description 3...

Page 495: ...gister and the udc ahb Subsystem is connected to a USB 1 1 host controller then after speed enumeration these bits indicates that the subsystem is operating in FS mode 2 b01 Besides if SPD states HS a...

Page 496: ...dicates that a reset is detected on the USB Note If the application didn t serve this interrupt the UDC AHB subsystem returns a NAK handshake for all transactions except the 8 SETUP packet bytes from...

Page 497: ...ven in Table 405 Note After checking this register the application must clear the interrupt by writing a b1 to the corresponding bit 23 8 10 Endpoint interrupt mask register The endpoint interrupt mas...

Page 498: ...For example after a SETUP packet has been decoded as a valid command by the application then the application must set the CNAK bit to clear the NAK bit The application also must clear the NAK bit thro...

Page 499: ...rring them to application memory snoop mode Note This bit is reserved for in endpoints only 01 F 1 h0 Flush the TxFIFO Setting this bit it flushes the TxFIFO Note This bit is reserved for out endpoint...

Page 500: ...d in slave only mode In DMA mode the application must check the status from the endpoint data descriptor 10 TDC 1 h0 Transmit DMA completion If set this bit indicates that transmit DMA has been comple...

Page 501: ...cket reception This 2 bit field states that if an out packet has been received by the endpoint The type of the incoming data is given by encoding 2 b00 None 2 b01 Data 2 b10 SETUP data 8 bytes 2 b11 R...

Page 502: ...These 2 bits indicate the initial data PID of the packet received that is available in the RxFIFO for an high bandwidth ISO transaction according to encoding 2 b00 DATA0 2 b01 DATA1 2 b10 DATA2 2 b11...

Page 503: ...the endpoint characteristics Table 410 Endpoint maximum packet size buffer size register bit assignments Bit Name Reset value Description 31 16 BUFF SIZE 16 h0000 Buffer size required for this endpoin...

Page 504: ...e 10 07 ConfNumber 4 h0 Configuration number to which this endpoint belongs 06 05 EPType 2 h0 Endpoint type The possible options are 2 b00 Control 2 b01 Isochronous 2 b10 Bulk 2 b11 Interrupt 04 EPDir...

Page 505: ...data transfer rates with the PHY interfaces above It supports both half duplex and full duplex operation In half duplex operation CSMA CD protocol is provided Programmable frame length to support bot...

Page 506: ...particular the AHB master interfaces with the DMA controller and converts the internal DMA request cycles into AHB cycles Both fixed burst length SINGLE INCR4 INCR8 INCR16 and unspecified burst lengt...

Page 507: ...er whereas buffer status is maintained in the relevant descriptor 24 3 4 Transmit and receive FIFO The Transmit FIFO TxFIFO buffers data read from system memory by the DMA before transmission by the M...

Page 508: ...list is written into DMA Register3 Receive Descriptor List Address Section 24 7 6 and Register4 Transmit Descriptor List Address Section 24 7 7 respectively Each descriptor list both for transmission...

Page 509: ...n along with control bits for controlling the descriptor structure and the frame being transferred Transmit Descriptor 1 TDES1 Table 415 it contains the data buffer sizes Transmit Descriptor 2 TDES2 T...

Page 510: ...ing and CRC to a frame shorter that 64 bytes and the CRC field is added despite the state if the DC bit TDES0 27 Valid only if TDES0 28 is set 25 TTSE Reserved 24 Reserved 23 22 CIC Checksum Insertion...

Page 511: ...the logical OR of the following bits of this descriptor 1 2 8 9 10 11 13 and 14 14 JT Jabber Timeout If set it indicates that the MAC transmitter has experienced a jabber timeout 13 FF Frame Flushed I...

Page 512: ...Buffer 2 Size These 13 bit field reports the size in bytes of the second data buffer Note This field is not valid if TDES0 20 is set 15 13 Reserved 12 00 TBS1 Transmit Buffer 1 Size These 13 bit fiel...

Page 513: ...If cleared the descriptor is owned by the host 30 AFM Destination Address Filter Fail If set it indicates a frame that failed in the DA filter in the MAC core 29 16 FL Frame Length These 14 bit field...

Page 514: ...as a non integer multiple of bytes odd nibbles Valid only in MII mode 01 CE CRC Error 00 Rx MAC address If set it indicates that the Rx MAC address value register1 to register15 matched the DA field o...

Page 515: ...e PHY 7 Write to DMA register6 operation mode Section 24 7 9 setting bits 1 SR and 13 ST to start reception and transmission respectively 13 Reserved 12 00 RBS1 Receive Buffer 1 Size These 11 bit fiel...

Page 516: ...from the MAC Core as a result of various events in the optional modules in it for example MMC and PMT modules These interrupt events are combined with events in the DMA on the sbd_intr_o signal Infac...

Page 517: ...14 32 h0 Status Register Register 6 0x1018 32 h0 Operation Mode Register Register 7 0x101C 32 h0 Interrupt Enable Register Register 8 0x1020 32 h0 Missed Frame And Buffer Overflow Counter Register 0x1...

Page 518: ...MAC UNIV MAC global registers summary below Table 424 MMC MAC management counters registers Name Offset Reset Value Description Register 64 0x0100 32 h0 Mmc_cntrl establishes the operating mode of MMC...

Page 519: ...of preamble and retried frames Register 78 0x0138 32 h0 Tx1024tomaxoctects_gb is the number of good and bad frames transmitted with length between1024and mqaxsize inclusive bytes exclusive of preambl...

Page 520: ...number of bytes received exclusive of preamble only in good frames Register 99 0x018C 32 h0 Rxbroadcastframes_g is the number of good broadcast frames received Register 100 0x0190 32 h0 Rxmulticastfra...

Page 521: ...ive bytes exclusive of preamble Register 112 0x01C0 32 h0 Rx1023tomaxoctects_gb is the number of good and bad frames transmitted with length between 1023 and maxsize inclusive bytes exclusive of pream...

Page 522: ...and 32 and any other value will result in undefined behavior DSL This 5 bit field specifies the number of Word Dword Long depending on 32 64 128 bit bus to skip between two unchained descriptors If D...

Page 523: ...register which enables the receive DMA to check for new descriptors The Receive Poll Demand bit assignments are given in Table 427 RPD When these bits are written with any value the DMA reads the cur...

Page 524: ...is given 24 7 8 Status register Register 5 DMA The Status is a RO register which contains all the status bit that the DMA reports to the host and it is usually read by the software driver during an in...

Page 525: ...ments Bit Name Reset Value Type Description 31 29 Reserved RO Read undefined 28 GPI 1 h0 RO MAC PMT Interrupt 27 GMI 1 h0 RO MAC MMC Interrupt 26 Reserved RO Read undefined 25 23 EB 3 h0 RO Error bits...

Page 526: ...g data transfer by RxDMA 1 b1 During data transfer by TxDMA 1 b0 During write transfer 1 b1 During read transfer 1 b0 During data buffer access 1 b1 During descriptor access Table 432 TS filed bit ass...

Page 527: ...signments Value State Description 3 b000 Stopped Reset or stop reception command issued 3 b001 Running Fetching receive transfer descriptor 3 b010 Reserved 3 b011 Running Waiting for receive packet 3...

Page 528: ...ster and DMA disables all its bus accesses ETI If set it indicates that the frame to be transmitted was fully transferred to MAC RWT This bit is set when a frame with a length greater than 2048 bytes...

Page 529: ...meaning that the transmitter had been excessively active Transmission is then aborted and placed in Stopped state causing the bit 14 in TDES0 to be set TU If set it indicates that the Next Descriptor...

Page 530: ...on mode register bit assignments Bit Name Reset Value Type Description 31 22 Reserved RO Read undefined 21 SF 1 h0 RW Store and Forward 20 FTF 1 h0 RW Flush Transmit FIFO 19 17 Reserved RW Read undefi...

Page 531: ...e FIFO at which the flow control in both HD and FD is de asserted after activation according to encoding below RFA This 2 bit field controls the threshold that is fill level of Receive FIFO at which t...

Page 532: ...his bit the receive process is placed in the Running state and the DMA attempts to acquire the descriptor from the Receive List and process incoming frames Descriptor acquisition is attempted from the...

Page 533: ...13 FBE 1 h0 RW Fatal bus error interrupt enable 12 11 Reserved RO Read undefined 10 ETE 1 h0 RW Early transmit interrupt enable 09 RWE 1 h0 RW Receive watchdog timeout enable 08 RSE 1 h0 RW Receive st...

Page 534: ...ansmit Buffer Address is a RO register which points to the current transmit buffer address being read by the DMA This pointer is updated by DMA during operation 24 7 15 Current host receive buffer add...

Page 535: ...be set in order to transmit jumbo frames IFG Note This 3 bit field controls the minimum inter frame gap between frames during transmission according to encoding below Table 443 MAC configuration regi...

Page 536: ...ck to work properly DM Setting this bit the MAC operates in a full duplex mode where it can transmit and receive simultaneously Note This bit is RO with default value of 1 b1 in full duplex only confi...

Page 537: ...state machine is deferred for more than 24 288 bit times Note This bit is applicable only to half duplex mode and it is reserved RO in full duplex only configuration TE Setting this bit transmit state...

Page 538: ...Core forwards the received frame to the application and with the updated received frame status word Receive Descriptor 0 RDES0 section 1 2 3 1 depending on the SA address comparison SAIF Setting this...

Page 539: ...he values programmed in DA registers HUC Setting this bit the MAC performs destination address filtering of received unicast frames according to the hash table as set in Register2 MAC and Register3 MA...

Page 540: ...5 bit field selects the desired MII register in the selected PHY device CR This 3 bit field allows selection of frequency range of CSR clock provided as input by the application and it is used to set...

Page 541: ...by the MAC during a PHY Read operation 24 7 21 MII data register Register5 MAC The MII data is a register which stores the 16 bit write data to be written to the PHY register located at the address in...

Page 542: ...e above and slot time is the time taken to transmit 512 bits 64 bytes on the MII interface Note The threshold value specified by PLT should be always greater than the Pause Time PT field UP Setting th...

Page 543: ...s bit will continue to be set meaning that a frame transmission is in progress After the completion of Pause control frame transmission the MAC will clear this bit 24 7 23 VLAN tag register Register7...

Page 544: ...the incoming frame passes the address filtering set by the command register and if the CRC 16 matches the incoming examined pattern then it means that a wake up frame is received 24 7 25 PMT control...

Page 545: ...was generated due to the reception of a wake up frame This bit is cleared by a read into this register 05 1 h0 RW Magic packet received If set it indicates that the power management event was generat...

Page 546: ...gh whenever an interrupt is generated in the MMC Interrupt register see section MMC Receive Interrupt Register This bit is cleared whenever the bit in the interrupt register is cleared 03 1 h0 RO PMT...

Page 547: ...s 6 bit field controls masking of each of the MAC address byte according to encoding below Setting a bit the corresponding byte of the received SA DA is not compared with the contents of MAC Address1...

Page 548: ...d transmitted frames that is number of bytes transmitted number of good and bad frames transmitted number of frames received with CRC error and so on These MMC registers also include a control registe...

Page 549: ...1 h0 The bit is set when the rxwatchdog error counter reaches half the maximum value 22 1 h0 The bit is set when the rxvlanframes_gb counter reaches half the maximum value 21 1 h0 The bit is set when...

Page 550: ...alf the maximum value 05 1 h0 The bit is set when the rxcrcerror counter reaches half the maximum value 04 1 h0 The bit is set when the rxmulticastframes_g counter reaches half the maximum value 03 1...

Page 551: ...ximum value 10 1 h0 The bit is set when the txunicastframes_gb counter reaches half the maximum value 09 1 h0 The bit is set when the tx1024tomaxoctects_gb counter reaches half the maximum value 08 1...

Page 552: ...rxcarriererror counter reaches half the maximum value 18 1 h0 The bit is set when the rxexesscol counter reaches half the maximum value 17 1 h0 The bit is set when the rxlatecol counter reaches half t...

Page 553: ...transmit clock on MII_CLK when it operates at 100 Mbps or 10 Mbps respectively The frequency of clock clk_rx_i is same as receive clock MII_RX_CLK generated by the external PHY The PHY outputs a 25 MH...

Page 554: ...HS_Media independent interface MII RM0082 554 844 Doc ID 018672 Rev 1 Figure 56 Clocking scheme for MAC AHB...

Page 555: ...e baseline JPEG standard ISO IEC 10918 1 Single clock per pixel encoding decoding Support for up to four channels of component color 8 bit channel pixel depths Programmable quantization tables up to f...

Page 556: ...25 3 1 Block diagram The block diagram of the JPGC is shown in Figure 58 Figure 58 JPGC block diagram AHB Master AHB Slave DMAC JPEG Codec In te rn a l m e m o rie s A H B M a ste r A H B S lave A H B...

Page 557: ...8 1 Also JFIF images the de facto standard used to encoded JPEG images is supported Before any coding process can start the codec core together with the DMAC and the Internal Memories must be programm...

Page 558: ...or encoding HuffMin HuffBase and HuffSymb memories are used for decoding 25 4 Programming model 25 4 1 Register map The JPGC can be fully configured by programming its 32 bits wide registers which can...

Page 559: ...2 h0 Codec Core Register 6 JPGCReg7 0x1C RW 32 h0 Codec Core Register 7 Table 470 JPGC codec controller registers Name Offset Type Reset value Description JPGC Control Status 0x00 RW 32 h0 Codec contr...

Page 560: ...ng the process itself 25 4 4 JPGCReg1 register This register defines several parameters for the image format and the coding process Table 472 JPGC internal memories Name Offset Type Reset value Descri...

Page 561: ...hen set this bit enables restart marker processing The ECS encoder inserts restart markers every NRST 1 minimum coded units Nf Number of color components in the source image minus 1 there can be from...

Page 562: ...is ignored if the Re bit in JPGC Reg1 is not set 25 4 7 JPGCreg4 7 register These registers describe the composition of a Minimum Coded Unit MCU As specified in the ISO document for the baseline algor...

Page 563: ...ing of the AC coefficients in the data units belonging to the color component i Since only two AC tables are allowed in the baseline algorithm 1 bit is sufficient for this field HDi This value defines...

Page 564: ...e The content of this register is cleared automatically when a new coding process starts NRX Number of bytes sent from FIFO In to the Codec Core This register is cleared when a new encoding process st...

Page 565: ...t is 0 EN Burst Count Enable Active High BTF Number of burst transfer sent by TX FIFO before controller will set interrupt 25 4 12 DMAC registers See Chapter 19 BS_DMA controller for a detailed descri...

Page 566: ...The tables occupy contiguous memory locations The memory map of the quantization memory is shown in Table 484 For decoding with header parsing no quantization table programming is required because th...

Page 567: ...e table can be up to 64 x 9 bit words its memory map is shown in Table 486 When decoding with header processing this table is automatically programmed by the codec core while in the case of ECS only d...

Page 568: ...odes for each of the 16 possible lengths that the specification allows This represents the first 16 bytes of each DC table and AC table address block in the JPGCDHTMem memory Vi value associated with...

Page 569: ...y 162 Huffman codes are required for the encoding the AC run length codes and 12 for the DC coefficients The location of the Huffman codes for the 162 run length codes in an AC table is shown in Table...

Page 570: ...is shown inTable 491 140 149 Huffman code of run lengths E 1 to E A 150 159 Huffman code of run lengths F 1 to F A 160 Huffman code of EOB 161 Huffman code of ZRL 162 167 FFF 168 175 FD0 FD7 Table 49...

Page 571: ...rates 576 Kbps and 1 152 Mbps Fast infrared FIR with rate 4 Mbps Provides a transceiver interface compliant to all IrDA transceivers with configurable polarity of TX and RX signals Integrates half dup...

Page 572: ...IrDA controller switches to the reception state and sets the RXS bit of the IrDA_STAT register Section 26 5 8 then a signal detected interrupt SD_INT Section 26 4 is generated Besides if the synchroni...

Page 573: ...d re adjusted if needed every following rising edge FIR 4PPM demodulation The preamble field PA of the synchronized RX signal is used by the receiver to establish phase lock by means of a DPLL digital...

Page 574: ...lse which creates the pulses of the TX signal during transmission The two signals are obtained from the same irda_clk clock signal by using cascaded clock dividers so the resulting frequencies are fen...

Page 575: ...mmunication one buffer is used for both transmission and reception The FIrDA controller generates the following request signals to control the data transfer to and from memory These signals can either...

Page 576: ...ved bytes of the frame are shifted from the wrapper unit to the FIFO where the data is buffered The received bytes are counted by a 12 bit counter and that value can be read by software in the receive...

Page 577: ...ion state it indicates that the current frame has not been sent completely This can be due to either a FIFO underflow see Section 26 3 6 or an abort by software Note FD_INT must have a lower priority...

Page 578: ...IrDA_RXD E3 IrDA_TXD F3 Table 496 FIrDA controller control and status registers summary Name Offset Type Reset value Description IrDA_CON 0x10 RW 32 h0 IrDA control IrDA_CONF 0x14 RW 32 h00020EA6 IrD...

Page 579: ...ype Reset value Description Table 499 IrDA_CON register bit assignments Bit Name Reset value Description 31 01 Reserved Read undefined Write should be zero 00 RUN 1 h0 Enable FIrDA controller Enable t...

Page 580: ...rt a burst size of 2 words 15 13 Reserved Read undefined Write should be zero 12 00 RATV 13 h0EA6 Reception abort timer value This 13 bit field indicates the reception abort timer value according to t...

Page 581: ...according to the encoding 12 b000001000110 70 bytes default 12 b000010000110 134 bytes 12 b000100000110 262 bytes 12 b001000000110 518 bytes 12 b010000000110 1030 bytes 12 b100000000110 2054 bytes Not...

Page 582: ...ts the decrement value of the fractional divider following the formula DEC L K where L and K values are listed in Table 492 15 08 INC 8 h0 Increment value of fractional divider This 8 bit field indica...

Page 583: ...Reset value 12 b000000000001 2 data bytes 12 b000000000010 3 data bytes 12 b100000000001 2050 data bytes Any other value Reserved Note The number of transmitted bytes is data size the information byte...

Page 584: ...writing a 1 b0 clears the relevant interrupt 26 5 14 IrDA_RIS register The IrDA_RIS Raw Interrupt Status is a RO register which reflects the current raw status value of the corresponding interrupt be...

Page 585: ...tected raw interrupt status 1 b0 No interrupt 1 b1 Interrupt pending 06 FI 1 h0 Frame invalid raw interrupt status 1 b0 No interrupt 1 b1 Interrupt pending 05 SD 1 h0 Signal detected raw interrupt sta...

Page 586: ...atus 1 b0 No interrupt 1 b1 Interrupt pending 05 SD 1 h0 Signal detected masked interrupt status 1 b0 No interrupt 1 b1 Interrupt pending 04 FT 1 h0 Frame transmitted masked interrupt status 1 b0 No i...

Page 587: ...0 clears a pending request and disables further requests 04 FT 1 h0 Frame transmitted interrupt clear 03 BREQ 1 h0 BREQ interrupt clear 02 LBREQ 1 h0 LBREQ interrupt clear 01 SREQ 1 h0 SREQ interrupt...

Page 588: ...roller RM0082 588 844 Doc ID 018672 Rev 1 01 SREQEN 1 h0 Single request DMA enable 00 LSREQEN 1 h0 Last single request DMA enable Table 513 IrDA_DMA register bit assignments continued Bit Name Reset v...

Page 589: ...mber Provides standard asynchronous communication bits start stop and parity which are added prior transmission and removed on reception Supplies independent masking of transmit or receive FIFO receiv...

Page 590: ...oss the APB Interface nUARTRST PCLK PRESETn PSEL PENABLE PWRITE PADDR 11 2 PWDATA 15 0 PRDATA 15 0 UARTCLK APB interface and register block UARTRXDMACLR UARTTXDMACLR UARTRXDMASREQ UARTRXDMABREQ UARTTX...

Page 591: ...gic performs parallel to serial conversion on the data read from the Transmit FIFO The control logic outputs the serial bit stream beginning with a start bit followed by data bits with the LSB first a...

Page 592: ...s the logical OR of the individual outputs The interrupts from UART1 to UART5 are further combined to generate a single interrupt at the RAS interface The individual interrupt source can be determined...

Page 593: ...the FIFOs are disabled and there is no data in the transmitter single location The interrupt is then cleared by performing a single write to the Transmit FIFO or by clearing the interrupt writing a 1...

Page 594: ...addition to reserved locations within the CSRs address space Table 518 offset addresses from 0x080 to 0xFDC are reserved for test purposes as well as for future extensions All these locations must no...

Page 595: ...tional baud rate UARTLCR_H 0x02C 16 RW 16 h0 Line control UARTCR 0x030 16 RW 16 h0300 UART control Table 518 UART control and status register summary continued Name Offset Width bit Type Reset value D...

Page 596: ...from UARTDR Section 27 4 1 prior to reading UARTRSR The status information for overrun is set immediately when an overrun condition occurs The UARTRSR bit assignments are given in Table 522 In contra...

Page 597: ...it in the UARTLCR_H register If FIFOs are disabled RXFF is set when the receive holding register is full whereas FIFOs enabled it is set when the receive FIFO is full 05 TXFF 1 h0 Transmit FIFO full T...

Page 598: ...f the current character is complete Note The minimum divide ratio is 1 and the maximum is 65535 that is 216 1 When UARTIBRD 65535 16 hFFFF UARTFBRD must not be greater than zero Some typical bit rates...

Page 599: ...00 0 16 16 h001A 115200 0 16 16 h0027 76800 0 16 16 h0034 57600 0 16 16 h004E 38400 0 16 16 h009C 19200 0 16 16 h00D0 14400 0 16 16 h0138 9600 0 16 16 h01A1 7200 0 08 16 h0271 4800 0 16 h04E2 2400 0 1...

Page 600: ...two stop bits being received 02 EPS 1 h0 Even parity select This bit allows to select either an even or an odd parity generation and checking during transmission and reception which checks for an even...

Page 601: ...flow control is enabled and data is only transmitted when nUARTCTS signal is asserted 14 RTSEn 1 h0 RTS hardware flow control enable Setting this bit the RTS hardware flow control is enabled and data...

Page 602: ...ted based on a transition through a level rather than being based on the level that is when the fill level progresses through the trigger level The UARTIFLS bit assignments are given in Table 531 08 T...

Page 603: ...3 4 full 3 b100 7 8 full Any other value Reserved 02 00 TXIFLSEL 3 h12 Transmit interrupt FIFO level select This 3 bit field allows to set the trigger points for the transmit interrupt according to e...

Page 604: ...5 Table 532 UARTIMSC register bit assignments continued Bit Name Reset value Description Table 533 UARTRIS register bit assignments Bit Name Reset value Description 15 11 Reserved Read as zero 10 OER...

Page 605: ...tatus 03 DSRMMIS 1 h0 nUARTDSR modem masked interrupt status see Section 27 5 02 DCDMMI S 1 h0 nUARTDCD modem masked interrupt status see Section 27 5 01 CTSMMIS 1 h0 nUARTCTS modem masked interrupt s...

Page 606: ...Write should be zero 02 DMAONERR 1 h0 DMA on error Setting this bit the DMA receive request outputs UARTRXDMASREQ or UARTRXDMABREQ are disabled when UART error interrupt is asserted 01 TXDMAE 1 h0 Tr...

Page 607: ...speed mode data rates up to 3 4 Mb s Provides clock synchronization Supports either master only in a single master environment or slave I2 C operation mode Supports only slave operation in multi mast...

Page 608: ...d Receiving Protocol START Byte Transfer Protocol START and STOP condition protocol When the bus is IDLE both the SCL serial clock and SDA serial data signals are pulled high through external pull up...

Page 609: ...e bits 7 to 3 notify the slaves that this is a 10 bit transfer followed by the next two bits 2 to 1 which set the bit 9 and 8 of the 10 bit slave address The LSB of the first byte is the RW bit Table...

Page 610: ...te with the same slave or with a different slave START byte transfer protocol The START byte transfer protocol is set up for systems that do not have an on board dedicated I2C hardware module In this...

Page 611: ...t of data to the transmit FIFO buffer Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers continuously that is when the FIFO begins to empty another DMA...

Page 612: ...protocol also allows multiple masters to reside on the I2C bus which requires the masters to arbitrate for ownership According to this specification the I2C controller provided by the device supports...

Page 613: ...r operation When another master addresses the I2C controller to send its data the I2C controller acts as a slave receiver and the following steps occur The other master initiates an I2C transfer with...

Page 614: ...n a slave Write to the IC_TAR register Section 28 6 4 the address of the I2 C device to be addressed by the I2 C controller as a master 10 bit field IC_TAR It also indicates whether adding a START BYT...

Page 615: ...b0 meaning a write operation Subsequently a read command may be issued by writing don t cares to the lower byte of the IC_DATA_CMD register and a b1 should be written to the CMD bit As data is transmi...

Page 616: ...of the next clock period However if another master is holding the SCL line to b0 then the master goes into a high wait state until the SCL clock line transitions to b1 All masters then count off thei...

Page 617: ...General call request received Indicates that a general call request was received refer to Section 28 3 2 I2C protocols on page 608 The I2C controller stores the received data in the Receive buffer STA...

Page 618: ...call command has been issued Disabling the I2 C reverts it back to normal operation if the processor attempts to issue read command before a RD_REQ is serviced Anytime this bit is set the contents of...

Page 619: ...en the receive buffer was completely filled to IC_RX_BUFFER_DEPTH and more data arrived The data is lost RX_UNDER Receive buffer empty This bit is set when the processor attempts to read the receive b...

Page 620: ...ection 28 6 17 0x038 8 RW 8 h00 I2 C receive FIFO threshold IC_TX_TL Section 28 6 18 0x03C 8 RW 8 h00 I2 C transmit FIFO threshold IC_CLR_INTR Section 28 6 19 0x040 1 RO 1 b0 Clear combined and Indivi...

Page 621: ...078 4 RO 4 h0 Receive FIFO Level 0x07C Reserved IC_TX_ABRT_SOURCE Section 28 6 24 0x080 16 RW 16 h0 I2C Transmit Abort Status 0x084 Reserved IC_DMA_CR Section 28 6 25 0x088 2 RW 2 h0 DMA Control IC_DM...

Page 622: ...speed mode operation perform combined format transfers in 7 or 10 bit addressing mode split for 7 bit perform a read operation with a 10 bit address Split operations are broken down into multiple I2...

Page 623: ...controls at which speed the I2 C controller operates according to the encoding b00 Illegal b01 Standard 100 kbit s b10 Fast 400 kbit s b11 High 3 4 Mbit s default If the device is configured for fast...

Page 624: ...master according to the encoding below 1 b0 7 1 b1 10 11 SPECIAL RW 1 h0 Perform a general call or start byte I2 C command This bit indicates whether software would like to either perform a general c...

Page 625: ...ter 0x010 The IC_DATA_CMD is a RW register which contains the I2 C Rx Tx data buffer and related read write command The IC_DATA_CMD bit assignments are given in Table 546 Table 544 IC_SAR register bit...

Page 626: ...ller Reading this bit returns b0 Attempting to perform a read operation after a general call command has been sent results in TX_ABRT unless the SPECIAL bit in IC_TAR register see Section 28 6 4 has b...

Page 627: ...ecimal SCL high time actual s 100 2 4 16 h0008 d8 4 00 100 6 6 4 16 h001B d27 4 09 100 10 4 16 h0028 d40 4 00 100 75 4 16 h012C d300 4 00 100 100 4 16 h0190 d400 4 00 100 125 4 16 h01F4 d500 4 00 100...

Page 628: ...ck frequency MHz SCL low time required min s IC_SS_SCL_LCNT hex decimal SCL low timeactual s Table 551 IC_FS_SCL_HCNT register bit assignments Bit Name Type Reset value Description 15 00 IC_FS_SCL_HCN...

Page 629: ...ws to set the high period of the SCL clock for high speed mode The IC_HS_SCL_HCNT bit assignments are given in Table 555 Table 553 IC_FS_SCL_LCNT register bit assignments Bit Name Type Reset value Des...

Page 630: ...he IC_ENABLE Section 28 6 21 register being set to b0 Write at other times has no effect 2 This register must be set before any I2 C bus transaction can take place in order to ensure proper I O timing...

Page 631: ...Table 557 IC_HS_SCL_LCNT register bit assignments Bit Name Reset value Description 15 00 IC_HS_SCL_LCNT 16 h00 1b SCL clock low period count for high speed This 16 bit field states the SCL clock low p...

Page 632: ...OP_DET RO 1 h0 08 R_ACTIVITY RO 1 h0 07 R_RX_DONE RO 1 h0 06 R_TX_ABRT RO 1 h0 05 R_RD_REQ RO 1 h0 04 R_TX_EMPTY RO 1 h0 03 R_TX_OVER RO 1 h0 02 R_RX_FULL RO 1 h0 01 R_RX_OVER RO 1 h0 00 R_RX_UNDER RO...

Page 633: ...ocol does not care whether it is a START or RESTART because both conditions start from the IDLE state and send the message to all the slaves on the bus 28 6 17 IC_RX_TL register 0x038 The IC_RX_TL is...

Page 634: ...entries in the receive FIFO of the I2 C controller which defines the RX_FULL interrupt threshold as RX_TL 1 The RX_TL valid range is 0 8 h00 to 255 8 hFF resulting in threshold ranging from 1 to 256 A...

Page 635: ...gister 0x06C The IC_ENABLE is a RW register which allow enabling disabling the I2 C controller The IC_ENABLE bit assignments are given in Table 566 Table 564 IC_CLR_INTR register bit assignments Bit N...

Page 636: ...g the I2 C controller stops as well as deletes the contents of the transmit buffer after the current transfer is complete If the module was receiving the I2 C controller stops the current transfer at...

Page 637: ...ed whenever the processor reads it or when the processor issues a clear signal to all interrupts The IC_TX_ABRT_SOURCE bit assignments are given in Table 569 03 RFNE 1 h0 Receive FIFO not empty If set...

Page 638: ...4 3 or if ABRT_SLV_ARBLOST bit in this register is also set the slave transmitter has lost arbitration 11 ARB_MASTER_DIS RW 1 h0 Attempt to use disabled master If set this bit indicates that user atte...

Page 639: ...ral call GCALL and no slave on the bus responded with an acknowledgement 03 ABRT_TXDATA_ NOACK RW 1 h0 Master receive acknowledge If set this bit indicates that the master has received an acknowledgem...

Page 640: ...the receive FIFO DMA channel Otherwise bit cleared it is disabled Table 571 IC_DMA_TDLR register bit assignments Bit Name Reset value Description 15 03 Reserved Read undefined Write should be zero 02...

Page 641: ...BUFFER_DEPTH RO 8 h07 Receive buffer depth This 8 bit field reports the receive buffer depth according to the encoding 8 h00 Reserved 8 h01 2 8 h02 3 8 hFF 256 07 ADD_ENCODED_PARA MS RO 1 h1 Add encod...

Page 642: ...the I2 C controller according to the encoding 2 b00 Reserved 2 b01 Standard 2 b10 Fast 2 b11 High 01 00 APB_DATA_WIDTH RO 2 h1 Data width This 2 bit field indicates the APB data bus width according t...

Page 643: ...ge or up to 128 as 2 s power 2 4 8 INL 1 LSB DNL 1 LSB Programmable conversion speed from a minimum conversion time of 1 s Normal or enhanced mode In normal mode the conversion start upon CPU request...

Page 644: ...DOWN bit is cleared 1 b0 the ADC is switched off and next conversion requires again a start up time after setting the ENABLE bit in the ADC_STATUS_REG register 29 3 2 Enhanced mode In this mode ENM b...

Page 645: ...et value Type Description ADC_STATUS _REG 0x0000 16 16 h0 R W Status Register AVERAGE_REG 0x0004 16 16 h0 RO Report the data of requested conversion SCAN_RATE 0x0008 32 32 h0 R W Scan rate for enhance...

Page 646: ...annel 1 Data register Enhanced mode CH2_DATA 0x0038 11 11 h0 RO Channel 2 Data register Enhanced mode CH3_DATA 0x003C 11 11 h0 RO Channel 3 Data register Enhanced mode CH4_DATA 0x0040 11 11 h0 RO Chan...

Page 647: ...ference Voltage Note P Positive Reference Voltage 08 CONVERSION READY 1 h0 RO Conversion status If set this bit indicates that the requested conversion is completed and results are available In contra...

Page 648: ...ENABLE of the ADC_STATUS_REG register are set to 1 b1 03 01 CHANNEL SELECT 3 h0 RW Channel selection This 3 bit field allows to select one of the 8 analog input AIN channels according to encoding 3 b...

Page 649: ...o program the frequency of ADC clock The ADC_CLK_REG bit assignments are given in Table 580 Note This register can be written to only if both bit 8 CONVERSION READY and bit 0 ENABLE of the same regist...

Page 650: ...annel They have different bit assignments according to the setting of the bit 13 HIGH RESOLUTION on the register ADC_STATUS_REG Section 29 5 1 The register bit assignments when the bit is reset are gi...

Page 651: ...ion 17 VALID DATA 1 h0 RO VALID DATA bit 1 b0 CONVERSION DATA field not valid 1 b1 CONVERSION DATA field valid 16 10 RESERVED reserved 09 00 CONVERSION DATA 10 h0 RO Contain the result of the last con...

Page 652: ...the register bit is 1 then the particular IP in the fixed part will be connected to PL_GPIO If the register bit is 0 then RAS_GPIO will be connected to PL_GPIO The following modes can be selected by...

Page 653: ...mode a FSMC interface for NOR Flash connectivity b Boot Pins 30 1 3 Photoframe mode In this mode following IPs are present a FSMC interface for NAND Flash connectivity 16 bits 5 control signals b CLC...

Page 654: ...e I2S Block f TDM block capable of communicating with 8 external devices g SD SDIO MMC host controller h Fully configurable Telecom GPIO8 7 4 and GPIO10 9 0 30 1 7 HEND_WIFI_PHONE MODE HIGH END WI FI...

Page 655: ...0 CAMl_LCDw MODE 8 bit CAMERA without LCD In this mode following IPs are present a 8 Bit Camera interface b 9 x 9 Keyboard c 4 SPI I2C Control signals d Digital to Analog converter e I2S Block f TDM b...

Page 656: ...log converter f I2S Block g TDM block capable of communicating with 2 external devices h SD SDIO MMC host controller i Fully configurable Telecom GPIO8 5 4 and GPIO10 9 8 30 2 Maximum number of GPIOs...

Page 657: ...00_0000 0x98FF_FFFF FSMC 0x9900_0000 0x9900_0000 0x9FFF_FFFF RAS Registers 0xA000_0000 0xA000_0000 0xAFFF_FFFF APB Blocks Table 585 FSMC address space Address Space IP 0x8000_0000 0x83FF_FFFF NAND on...

Page 658: ...FFFF Static memory controller NAND Bank0 AHB 0x8400_0000 0x87FF_FFFF Static memory controller NAND Bank1 AHB 0x8800_0000 0x8BFF_FFFF Static memory controller NAND Bank2 AHB 0x8C00_0000 0x8FFF_FFFF Sta...

Page 659: ...00 1 h0 Timer A timers 1 2 Table 588 RAS Register 1 description Field Default Value Description Table 589 RAS Register 2 description Field Default Value Description 31 1 h0 This bit is used for confi...

Page 660: ...s of G8 G10 provide output data In input mode if this bit is 0 lower numbered G8 G10 set is active If this bit is 1 higher numbered G8 G10 set is active 22 05 18 h0 Reserved 04 1 h0 Determines if TDM_...

Page 661: ...r assignments Request RAS IP RAS_DMA_REQ 0 Not Used RAS_DMA_REQ 1 I2S RAS_DMA_REQ 2 TDM RAS_DMA_REQ 3 CAMERA RAS_DMA_REQ 4 Not Used RAS_DMA_REQ 5 Not Used RAS_DMA_REQ 6 Not Used RAS_DMA_REQ 7 Not Used...

Page 662: ...an one AHB cycle Main features of FSMC AHB slave interface Interfaces static memory mapped devices including RAM and Flash both NAND and NOR In case of Swims and Flash 8 and 16 bit wide it provides ex...

Page 663: ...han 32 bits In other cases OKAY response is returned The AHB interface does not support the following AHB features It does not generate SPLIT or RETRY responses Protection control is not implemented t...

Page 664: ...and R B is low the controller should wait until R B goes high 31 3 3 Asynchronous SRAM and NOR parallel Flash controller This block interfaces the AHB Interface block to external memory devices such...

Page 665: ...configuration registers are associated with each chip select and they allow to specify the type of external device SRAM or Flash as well as the associated timings i e how many HCLK cycles to complete...

Page 666: ...Description GenMemCtrl0 0x000 RW Controls of bank 0 GenMemCtrl_tim0 0x004 RW Timings of bank 0 GenMemCtrl1 0x008 RW Controls of bank 1 GenMemCtrl_tim1 0x00C RW Timings of bank 1 GenMemCtrl2 0x010 RW C...

Page 667: ...ribute memory mode 0x0B0 to 0x0BC Reserved Table 596 FSMC identification registers summary Name Offset Size Type Value Description GenMemCtrl_PeriphID0 0xFE0 8 RO 8 h90 Peripheral Identification GenMe...

Page 668: ...input pin of the Flash memory according to the encoding below 0 Disabled 1 Enabled default Note Wprot port is not available in SPEAr300 06 RstPwr Down 1 h1 Reset power down signal to Flash memory Thi...

Page 669: ...he BankEnable bit is b1 It follows that accessing the memory in such condition causes a HRESP to be ERROR on AHB Table 597 GenMemCtrl i register bit assignments continued Bit Name Reset value Descript...

Page 670: ...field is 4 b0000 default that is Tclr is one HCLK cycle 08 1 h0 Reserved Read undefined Write should be zero 07 EccPLen 1 h0 ECC page length This bit allows to define the page length of the NAND Flash...

Page 671: ...parity of a page of memory and to place the 3 byte result in an ECC table where it can be retrieved in order to check the consistency of the data The GenMemCtrl_ECCr i reports this ECC 3 byte result T...

Page 672: ...MemCtrlPCellID0 3 registers are four read only 8 bit registers The bit assignments are Bit Name Reset value Description 31 08 Reserved Read undefined Write should be zero 07 00 PartNumber0 8 h90 These...

Page 673: ...ng from oen wen high to end of cycle thiz timing from start of cycle and enable data out bus only for write mode Bit Name Reset value Description 31 08 Reserved Read undefined Write should be zero 07...

Page 674: ...k period 1 Thiz timing for thiz clock period About Thold_value the right value is Timing period tset twait Tclk FSMC parameters are TCS Clock cycles between Chip Selects 3 TCLK Hclk period TWAIT numbe...

Page 675: ...n Choose the biggest among tcs tcls TCS TCLK tar TCS TCLK tals tclr twh TCS TCLK treh TCS Thold TCLK tir tdh TCS Thold TCLK tset Tset int tset Dtoutdel TCLK Twait computation Chose the biggest among t...

Page 676: ...Twait 1 TCLK twhr Tset 1 TCS TCLK tclh thold Thold int thold trr Dtoutdel TCLK 1 Wait signal expected attribute memory Chose the biggest among talh tch twc Tset 1 Twait 1 TCLK trc Tset 1 Twait 1 TCLK...

Page 677: ...nterface taddr_st max between tavlh twhwl taddr_st Taddr_st int taddr_st Dtoutdel TCLK Thold_add int tlhax Dtoutdel TCLK Tdata_st int tllqv tdelout tdelin TCLK Taddr_st 1 tBusTurn is the max between t...

Page 678: ...ecification version 1 01 Meets MMC Specification version 3 31 and 4 2 Supports both DMA and Non DMA mode of operation Supports MMC Plus and MMC Mobile Card Detection Insertion Removal Password protect...

Page 679: ...BA Specification CARD INTERFACE SD_CLK Out 1 CLK to external card DATA In Out 8 SD1 SD4 SD8 Data line SDIO_CMD In Out 1 SD1 SD4 SD8 Command line SDIO_WP In 1 Active high SD card write protect SDIO_CD...

Page 680: ...ead data m_hwrite OUT Write Read Direction Indication m_hsize 2 0 OUT Size byte half word or word m_hburst 2 0 OUT Burst Size m_hready IN Ready signals m_htrans 1 0 OUT Transfer type m_hresp 1 0 IN Tr...

Page 681: ...mode Data2 output or Read wait optional SD8 mode Data2 output DATA2_OUT_EN OUT SD1 mode Read wait enable optional SD4 mode Data2 output enable or Read wait enable optional SD8 mode Data2 output enabl...

Page 682: ...al Sleep Clock to clk_sleep_in Input To use Internally generated Sleep Clock for Card Detection At the top connect both clk_sleep_in clk_sleep_out together rstahb_n IN External reset clk_sdram OUT clk...

Page 683: ...rd The host controller alternatively uses two dual port 4KB FIFOs for read data transferred from card to processor and write data transferred from processor to card transactions The DAT 0 7 control lo...

Page 684: ...river detects the card insertion or removal clear its interrupt statuses If Card Insertion interrupt is generated write logic 1 to Card Insertion in the Normal Interrupt Status register If Card Remova...

Page 685: ...ternal Clock Stable in the Clock Control register Repeat this step until Clock Stable is logic 1 4 Set SD Clock Enable in the Clock Control register to logic 1 Then the Host Controller starts to suppl...

Page 686: ...he case of no abort command go to step 4 4 Check Command Inhibit DAT in the Present State register Repeat this step until Command Inhibit DAT is set to logic 0 5 Set the value of command argument to t...

Page 687: ...te Status Return Status No Error Get Response Data Wait for Command Complete Int Command with Transfer Complete Int Wait for Transfer Complete Int Clr Transfer Complete Status Check Response Data Retu...

Page 688: ...ued command 4 Judge whether the command uses the Transfer Complete Interrupt or not If it uses Transfer Complete go to step 5 If not go to step 7 5 Wait for the Transfer Complete Interrupt If the Tran...

Page 689: ...lock Size Reg Set Block Count Reg Set Argument Reg Set Transfer Mode Reg Get Block Data Wait for Buffer Write Ready Int Clr Buffer Write Ready Status Set Block Data Wait for Transfer Complete Int Clr...

Page 690: ...In case of read from a card go to step 14 10 Then wait for Buffer Write Ready Interrupt 11 Write logic 1 to the Buffer Write Ready in the Normal Interrupt Status register for clearing this bit 12 Wri...

Page 691: ...Block Count Reg Set Argument Reg Set Transfer Mode Reg Set Command Mode Reg Wait for Command Complete Int Command Complete Int occur Clr Command Complete Status Get Response Data Wait for Transfer Com...

Page 692: ...errupt 8 Write logic 1 to the Command Complete in the Normal Interrupt Status register to clear bit 9 Read Response register and get necessary information of the issued command 10 Wait for the Transfe...

Page 693: ...y the 16 bit Block Count register If the Block Count Enable in the Transfer Mode register is set to logic 0 total data length is designated by not Block Count register but the Descriptor Table In this...

Page 694: ...to clear this bit 14 Write logic 1 to the ADMA Error Interrupt Status in the Error Interrupt Status register to clear this bit 15 Abort ADMA operation SD card operation should be stopped by issuing a...

Page 695: ...gument register TRMode 0x00C 16 Transfer mode register CMD 0x00E 16 Command register RESP0 0x010 32 Response register RESP1 0x014 32 RESP2 0x018 32 RESP3 0x01C 32 BufDataPort 0x020 32 Buffer data port...

Page 696: ...nnot be altered by software or any reset operation Write to these bits are ignored ROC Read Only Status These bits are initialized to zero at reset Writes to these bits are ignored RW Read Write Regis...

Page 697: ...Size in the Block Size register The Host Controller generates DMA Interrupt to request to update this register The HD sets the next system address of the next data position to this register When most...

Page 698: ...nsfer Mode register is set to 1 3 b000 4KB Detects A11 Carry out 3 b001 8KB Detects A12 Carry out 3 b010 16KB Detects A13 Carry out 3 b011 32KB Detects A14 Carry out 3 b100 64KB Detects A15 Carry out...

Page 699: ...ansaction has stopped Read operations during transfer return an invalid value and write operations shall be ignored When saving transfer context as a result of Suspend command the number of blocks yet...

Page 700: ...ble 1 b1 Enable 01 BLKCntEn 1 h0 RW This bit is used to enable the Block count register which is only relevant for multiple block transfers When this bit is logic 0 the Block Count register is disable...

Page 701: ...command fails the HC shall maintain its current state and the HD shall restart the transfer by setting Continue Request in the Block Gap Control Register Resume Command The HD re starts the data tran...

Page 702: ...1 Enable 02 Rsvd Reserved 01 00 RESTypeSel 2 h0 RW Response Type Select 2 b00 No Response 2 b01 Response length 136 2 b10 Response length 48 2 b11 Response length 48 check Busy after response Table 62...

Page 703: ...CR Register for memory R 39 8 RESP 31 0 R4 OCR Register OCR Register for I O R 39 8 RESP 31 0 R5 R5b SDIO Response R 39 8 RESP 31 0 R6 Published RCA response New published RCA 31 16 R 39 8 RESP 31 0 T...

Page 704: ...interrupt in the Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal Interrupt in the Normal Interrupt Status register The Software Reset For All in the Software Reset...

Page 705: ...and no current block transfers are being sent as a result of the Stop At Block Gap Request set to logic 1 A transfer complete interrupt is generated when this bit changes to 0 1 b1 Transferring data...

Page 706: ...e the next SD command Commands with busy signal belong to Command Inhibit DAT ex R1b R5b type Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal interrupt status register Note...

Page 707: ...r shall check support of DMA modes by referring the Capabilities register 2 b00 SDMA is selected 2 b01 32 bit Address ADMA1 is selected 2 b10 32 bit Address ADMA2 is selected 2 b11 64 bit Address ADMA...

Page 708: ...the Host System shall not supply SD bus voltage 3 b111 3 3 Flattop 3 b110 3 0 V Typ 3 b101 1 8 V Typ 3 b100 3 b000 Reserved 00 SDBPWR 1 h0 RW Before setting this bit the SD host driver shall set SD B...

Page 709: ...d Wait Control 1 b0 Disable Read Wait Control 01 CNTREQ 1 h0 RW This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request To cancel stop at the block gap set Stop...

Page 710: ...ecuting a transaction at the next block gap for non DMA SDMA and ADMA transfers Until the transfer complete is set to logic 1 indicating a transfer completion the HD shall leave this bit set to logic...

Page 711: ...RW Wakeup Event Enable On SD Card Insertion This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status register FN_WUS Wake up Support in CIS does not affect this bit 1...

Page 712: ...the SD Clock When setting multiple bits the most significant bit is used as the divisor But multiple bits should not be set According to the Physical Layer Specification the maximum SD Clock frequenc...

Page 713: ...shall be able to be read and written Clock starts to oscillate when this bit is set to logic 1 When clock oscillation is stable the HC shall set Internal Clock Stable in this register to logic 1 This...

Page 714: ...d Ready Buffer Write Ready Block Gap Event Transfer Complete 1 b1 Reset 1 b0 Work 01 SWRESCMD RWAC Only part of command circuit is reset The following registers and bits are cleared by this bit Presen...

Page 715: ...08 CDINT 1 h0 ROC Writing this bit to logic 1 does not clear this bit It is cleared by resetting the SD card interrupt factor In 1 bit mode the HC shall detect the Card Interrupt without SD Clock to s...

Page 716: ...if the Buffer Write Enable changes from 0 to 1 1 b0 Not Ready to Write Buffer 1 b1 Ready to Write Buffer 03 DMAINT 1 h0 RW1C This status is set if the HC detects the Host DMA Buffer Boundary in the B...

Page 717: ...second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap Control Register and data transfers completed After valid data is written to the SD ca...

Page 718: ...f the status 0 0 Interrupted by Another Factor Don t care 1 Response not received within 64 SDCLK cycles 1 0 Response Received Table 639 ERRIRQSTAT register bit assignments Bit Name Reset value Type D...

Page 719: ...ading logic 0 means that the HC is supplying power and no error has occurred This bit shall always set to be logic 0 if the HC does not support this function 1 b0 No Error 1 b1 Power Fail 06 DATAEBERR...

Page 720: ...ne to logic 1 level but detects logic 0 level on the CMD line at the next SDCLK edge then the HC shall abort the command Stop driving CMD line and set this bit to logic 1 The Command Timeout Error sha...

Page 721: ...bit is set to logic 0 the HC shall clear Interrupt request to the System The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to logic 1 The HD should cl...

Page 722: ...ERSTSEN 01 CMDCRCERSTSEN 00 CMDTOERSTSEN Table 642 ERRIRQSTATEN register bit assignments continued Bit Name Reset value Type Description Table 643 NIRQSIGEN register bit assignments Bit Name Reset val...

Page 723: ...erved 09 ADMAERSIGEN 1 b0 Masked 1 b1 Enabled 08 ACMD12ERSIGEN 07 CURLERSIGEN 06 DATAEBSIGEN 05 DATACRCERSIGEN 04 DATATOERSIGEN 03 CMDIDXERSIGEN 02 CMDEBERSIGEN 01 CMDCRCERSIGEN 00 CMDTOERSIGEN Table...

Page 724: ...ock data transfer is not started due to command error this bit is not set because it is not necessary to issue Auto CMD12 Setting this bit to logic 1 means the HC cannot issue Auto CMD12 to stop memor...

Page 725: ...er are Asynchronous Then bit 7 shall be sampled when driver never writing to the Command register So just before reading the Auto CMD12 Error Status register is good timing to set the bit 7 status bit...

Page 726: ...t High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz 1 b0 High Speed Not Supported 1 b1 High Speed Supported 20 Rsvd Reserved 19 ADMA2SUPP 1 h1 Hwinit 1 b1 ADMA2 support 1 b0...

Page 727: ...MHz 0x00 Get information via another method 07 TOCLKU 1 h1 Hwinit This bit shows the unit of base clock frequency used to detect Data Timeout Error 1 b0 kHz 1 b1 MHz 06 Rsvd Reserved 05 00 TOCLKFREQ 6...

Page 728: ...er bit assignments Bit Name Reset value Type Description 31 00 Rsvd Reserved Table 651 Maximum current value definition Register value decimal Current value 0 Get information through another method 1...

Page 729: ...Interrupt is generated 1 b0 no interrupt 00 FEACMDNE 1 h0 WO Force Event for Auto CMD12 NOT Executed 1 b1 Interrupt is generated 1 b0 no interrupt Table 652 ACMD12FEERSTS register bit assignments cont...

Page 730: ...Error 1 b1 Interrupt is generated 1 b0 No interrupt 04 FEDATATOER 1 h0 WO Force Event for Data Timeout Error 1 b1 Interrupt is generated 1 b0 No interrupt 03 FECMDIDXER 1 h0 WO Force Event for Command...

Page 731: ...ded by the block length 1 b1 Error 1 b0 No error 01 00 ADMAERST S 2 h0 RW ADMA Error State This field indicates the state of ADMA when error is occurred during ADMA data transfer This field never indi...

Page 732: ...the ADMA Error Interrupt is generated this register shall hold valid Descriptor address depending on the ADMA state The Host Driver shall program Descriptor Table on 32 bit boundary and set 32 bit bou...

Page 733: ...S register bit assignments Bit Name Reset value Type Description 15 08 Rsvd Reserved 07 00 SLTIRQSIG 8 h00 ROC These status bit indicate the logical OR of Interrupt signal and Wakeup signal for each s...

Page 734: ...and Lower 4 bits indicate the version 00 SD Host Specification version 1 0 01 SD Host Specification version 2 00 including only the feature of the Test Register 02 SD Host Specification version 2 00 i...

Page 735: ...le and dual panel mono super twisted nematic STN displays with 4 or 8 bit interfaces Supports single and dual panel color and monochrome STN displays Supports thin film transistor TFT color displays R...

Page 736: ...bus interface Dual panel monochrome STN panels 4 bit and 8 bit bus interface per panel Single panel color STN panels 8 bit bus interface Dual panel color STN panels 8 bit bus interface per panel 33 1...

Page 737: ...palettized 4 gray scales selected from 15 4 bpp palettized 16 gray scales selected from 15 You can program greater than four bpp for mono panels but using these modes does not make sense because the m...

Page 738: ...r panel STN single 3 MUSTN Mono upper panel STN dual and or single panel 4 MLSTN Mono lower panel STN single Table 663 shows which CLD 23 0 pins are used to supply the pixel data to the STN panel for...

Page 739: ...served Reserved CLD 15 Reserved CLSTN 0 Reserved Reserved Reserved MLSTN 0 CLD 14 Reserved CLSTN 1 Reserved Reserved Reserved MLSTN 1 CLD 13 Reserved CLSTN 2 Reserved Reserved Reserved MLSTN 2 CLD 12...

Page 740: ...ad AMBA AHB accesses INCR4 INCR8 and undefined length WORD bursts only OKAY response only 33 5 2 AHB master interface The AMBA AHB master interface transfers display data from a memory to the PrimeCel...

Page 741: ...input ports of the FIFOs are connected to the AMBA AHB interface and the output port feeds the pixel serializer Synchronization logic is used to transfer the pixel data from the AMBA AHB HCLK domain t...

Page 742: ...1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 4 p3 p2 p1 p0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 8 p1 p0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 16 p0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24 p0 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 743: ...22 21 20 19 18 17 16 bpp DMA FIFO Output Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1 p8 p9 p10 p11 p12 p13 p14 p15 p0 p1 p2 p3 p4 p5 p6 p7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 p4 p5 p6 p7 p0...

Page 744: ...n2 p1 Green2 p1 Green3 22 p0 Blue6 p1 Green1 p1 Green1 p1 Green2 21 p0 Blue5 p1 Green0 p1 Green0 p1 Green1 20 p0 Blue4 p1 Red4 p1 Red4 p1 Green0 19 p0 Blue3 p1 Red3 p1 Red3 p1 Red3 18 p0 Blue2 p1 Red2...

Page 745: ...ls This provides 15 gray scales for mono displays In the case of STN color displays the three color components red green and blue are gray scaled simultaneously which results in 3 375 15x15x15 colors...

Page 746: ...nterrupt The master bus error interrupt is asserted when an ERROR response is received by the master interface during a transaction with a slave When such an error is encountered the master interface...

Page 747: ...s stabilized a logic 1 is written to the LcdEn bit in the LCDControl Register Section 33 6 10 This enables the following signals into their active states CLLP CLCP CLFP CLAC CLLE The CLD 23 0 signals...

Page 748: ...674 Identification registers listed in Table 675 Mn display specific mSec Provided through SW Mn display specific mSec Provided through SW LCD On Sequence Min 0 ms Min 0 ms Minimum 0 ms Minimum 0 ms...

Page 749: ...ister Table 674 Color palette register Name Offset Type Width bit Reset value Description LCDPalette 0x200 to 0x3FC RW 32 undefined LCD color palette registers Table 675 Identification register Name O...

Page 750: ...e starting the next display line HBP can generate a delay of 1 256 pixel clock cycles 23 16 HFP 8 h0 Horizontal front porch is the number of CLCP periods between the end of active data and the rising...

Page 751: ...each frame The VBP count starts just after the vertical synchronization signal for the previous frame has been negated for active mode or the extra line clocks have been inserted as specified by the...

Page 752: ...1 The LPP field specifies the total number of lines or rows on the LCD panel being controlled LPP is a 10 bit value that allows 1 1 024 lines The register is programmed with the number of lines per L...

Page 753: ...nes on the falling edge of CLCP The IPC bit is used to select the edge of the panel clock on which pixel data is driven out onto the LCD data lines 12 IHS 1 h0 Invert horizontal synchronization 1 b0 C...

Page 754: ...s are output per CLCP cycle so the panel clock is 0 375 times You can bypass the pixel clock divider for TFT displays by setting the LCDTiming2 26 BCD bit 1 The data path latency forces some restricti...

Page 755: ...o 33 6 9 LCDIMSC register LCDIMSC is the interrupt mask set clear register Setting bits in this register enables the corresponding raw interrupt LCDRIS bit values to be passed to the LCDMIS Table 680...

Page 756: ...d when either of the DMA FIFOs have eight or more empty locations 15 14 Reserved do not modify read as zero write as zero 13 12 LCDVCOMP 2 h0 Generate interrupt at 2 b00 Start of vertical synchronizat...

Page 757: ...ono LCD uses 4 bits interface 1 b1 mono LCD uses 8 bits interface LcdMono8 has no meaning in other modes and must be programmed to 0 05 LCDTFT 1 h0 LCD is TFT 1 b0 LCD is an STN display use gray scale...

Page 758: ...Vertical compare Set when one of the four vertical regions selected through the LCD control register is reached 02 LNBU 1 h0 LCD next address base update mode dependent set when the current base addr...

Page 759: ...y When configured for big endian byte ordering this is reversed because bits 31 16 are the low numbered palette entry and bits 15 00 are the high numbered entry Table 686 LCDICR register bit assignmen...

Page 760: ...gisters are hard coded and the fields in the register determine the reset value 20 16 R 4 0 Red palette data 15 I Intensity bit Can be used as the LSB of the R G and B inputs to a 6 6 6 TFT display do...

Page 761: ...e Reset value Description 31 08 Reserved read as zero 07 04 Revision 4 h0 These bits read back as 0x0 03 00 Designer1 4 h4 These bits read back as 0x4 Bit Name Reset value Description 31 08 Reserved r...

Page 762: ...r bus error interrupt can be cleared by writing a logic 1 to the MBERROR bit within the LCDICR Register This action releases the master interface from its ERROR state to the start of FRAME state enabl...

Page 763: ...states but the CLD 23 0 signals remain LOW 3 When the signals in Step 2 have stabilized where appropriate the contrast voltage Vee this is not controlled or supplied by the CLCD is then applied 4 You...

Page 764: ...input from 2 sources LCD Timing Register2 selects between HCLK and 48MHz clock Figure 81 CLCD clock muxing scheme 48 MHz Register Block DMA FIFO LCD Control LCD Panel Palete RAM CLCDCLK HCLK CLCDCLKS...

Page 765: ...ster and slave mode of operation Programmable clock and synchronization signals generation in master mode Clock and synchornization signals recovery in slave mode Multiple clock source options with ma...

Page 766: ...LK HTRANS HBURST HSIZE HADDR HDATA 15 HSELreg HREADYx HRDATAx HRESPx HREADY HRDATA HRESP HADDR HSIZE HSELreg HSEL_am HSEL_sw HSEL_buf HADDR HSEL AHB GPIOs Regs Mux Decoder Defalut slave Int block Regs...

Page 767: ...ram Externally the TDM clock block is connected to the four customization clock pins PL_CLK1 PL_CLK2 PL_CLK3 PL_CLK4 of the device plus the CLK pin PL_GPIO35 that is used in slave mode PL_CLK1 outputs...

Page 768: ...ly the TDM synchro block is connected to SYNC0 to SYNC7 pins a SYNC1 to SYNC3 and SYNC0 if used master mode are generated from an internal counter and can take a predefined shape They can all be delay...

Page 769: ...tain a programmable number of timeslots please refer toTable 716 TDM_timeselot_NBR register Offset 0x38 Each timeslot 8 bit data can be used for switching or bufferization Action memory indicates what...

Page 770: ...Destination can be either the switching memory or the buffer memory or both In the reverse direction the TDM output can be in low impedance or high impedance on a timeslot basis When in low impedance...

Page 771: ...he processor about the bank position the MSB bit can be read in the Table 718 TDM_SYNC_GEN register Offset 0x40 When the last timeslot of a frame must be switched with the first timeslot of the next o...

Page 772: ...t rate usually 10ms 20ms or 30ms rate A packet consists of a number of frames given by theTable 717 TDM_Frame_NBR register Offset 0x3C Number of frames per packet must be same for all channels Hence i...

Page 773: ...data type using a single counter a frame counter is implemented From the above diagram the location where the sample will has to be stored inside the current buffer area is given by Frame counter for...

Page 774: ...ccessive frames of the same channel channel 0 considering the two wideband cases with odd memory bank used for buffering samples Narrowband companded Narrowband linear Odd bank Even bank 0000 Byte0 By...

Page 775: ...Odd bank Even bank 0000 Byte0 Byte1 Byte2 Byte3 Byte0 Byte1 Byte2 Byte3 LSB1 MSB1 LSB2 MSB2 S1 S2 S3 LSB3 MSB3 03FF 3800 3EFF 3000 3FFF 4000 43FF 7800 7EFF 7000 7FFF Ch0 Ch0 Ch4 Ch5 Ch4 Ch5 S4 LSB4 M...

Page 776: ...bank bit 2 The channel number programmed in 19 16 bits of Table 727 Action memory register and selected on the basis of number of channels given by 26 24 bits of the same Table 727 Action memoryregis...

Page 777: ...an be 8 16 or 32 bits The DOUT line can be high impedance when out of samples Data is always stored in 32 bit format in the buffer A shift left operation is possible to left align the data In master m...

Page 778: ...e played When the two banks are switched this can generate an interrupt or DMA transfer When this event occurs if the processer has not finished to process the previous input buffer and store the new...

Page 779: ...be reserved for the DAC In this case the input sampling frequency must be either 8 kHz standard TDM or 16 kHz when connecting wideband CODECs for instance The number of bits in a frame must be fixed b...

Page 780: ...order filter 2048kHz ouput 32 interpolation optional Integration 16 bit CPT Integration 16 bit CPT 0 5 0 5 Order 2 noise shaper Sign bit In this figure 8 kHz input data is first over sampled by the pr...

Page 781: ...n be programmed to function as SPI chip select I2C clock or simple general purpose output pins please refer to Table 723 I2S_CLK_CONF register Offset 0x50 and Table 721 I2S_CONF register Offset 0x4C r...

Page 782: ...re generating an interrupt The IT interrupt is then generated The purpose of such an interface is to supervise the hook detection of up to 8 SLICs Alternatively it can be used to debounce a switch or...

Page 783: ...uffer Memory 0x5004_0000 0x5004_0FFF Sync Memory 0x5005_0000 0x5005_0FFF I2S Bank 1 0x5005_1000 0x5005_1FFF I2S Bank 2 Table 702 Telecom registers Offset Type Name 0x00 RO BOOT 0x04 RW TDM_CONF 0x08 R...

Page 784: ...register is used by the CLK_GEN module It allows configuration of the internal clock that will be used as reference for the TDM 0x50 RW I2S_CLK_CONF 0x54 RW Interrupt mask 0x58 RO Interrupt status 0x...

Page 785: ...emories sw or buf through store_in 27 LBPD loopback from parallel data sw_data_out to sw_data_in and buf_data_out to buf_data_in When LBPD 0 no loopback is implemented When LBPD 1 the loopback is set...

Page 786: ...utput of the divider stage is then the input frequency divided by 2 D 15 0 1 02 Bypass when bypass 1 the osrc output is used as internal clock for the TDM logic Int_CLK when bypass 0 the divider outpu...

Page 787: ...R_Synt 3 PL_CLK4 CLKSM Isrc2 0 CLKSM inv tck2 Int_CLK 0 0 CLKo1 0 Int_CLK Internal_clock CLKo1 0 0 CLR_Pll2 ClkR_Synt 3 MIIC1 0 PL_CLK1 PL_CLK3 PL_CLK2 PL_GPIO 35 ClkR_osc1 PL_CLK4 Table 705 GPIO8_DIR...

Page 788: ...he value that will be out on the pins for GPIO10 block when they are in output mode Table 706 GPIO10_DIR register Offset 0x0C Bits Name Comments 31 10 Reserved When Dirx 0 the relevant GPIOx pin is se...

Page 789: ...om the pins connected to GPIO10 block Table 708 GPIO10_out register Offset 0x14 Bits Name Comments 31 10 Reserved The bits to be out on the respective pins if they are in output mode 09 Val9 08 Val8 0...

Page 790: ...1 10 Reserved Latched value from the respective pins 09 In9 08 In8 07 In7 06 In6 05 In5 04 In4 03 In3 02 In2 01 In1 00 In0 Table 711 IT_GEN register Offset 0x24 Bits Name Comments 31 24 Reserved 23 GP...

Page 791: ...tability of change 07 Ch3 1 Interrupt on change on pin 3 0 No interrupt on change on pin 3 06 P3 1 Interrupt when 8 bits are stable for pers_time after last change on P3 0 No interrupt on stability of...

Page 792: ...ched on this register This is the new value that was stable for more than pers_time RESET all 0 34 6 14 TDM_timeslot_NBR register This register informs about the number of timeslots contained in the f...

Page 793: ...ve channels in buffering mode Channels are opened in accordance with the contents of Action Memory Table 718 TDM_SYNC_GEN register Offset 0x40 Bits Name Comments 31 Nsh When Nsh 1 b1 the BUF memory is...

Page 794: ...nks frozen When BBfrz 0 the two buffer banks can toggle When BBfrz 1 the two banks are frozen The used bank is given by BBVal 25 nAHB_L The value to force for the lower buffer memory for the AHB nAHB_...

Page 795: ...rries wideband data Two pulses are required for the framesync generally every 62 5 s 18 17 Use3 These bits are used with Wb3 according to the following table Wb3 Use3 1 Use3 0 Synchro type 0 0 0 0 0 0...

Page 796: ...lay in byte between the SYNC1 and one of the previous channel Bdel1 1 Bdel1 0 Delay 0 0 No delay 0 1 1 byte 1 0 2 bytes 1 1 4 bytes 08 bdel1 Informs if the frame synch SYNC1 is for a delayed frame of...

Page 797: ...the PCM synchro SYNC0 must be in wideband type one additional pulse at the middle of the frame When Wb0 0 the PCM carries narrowband data Only one pulse is required for the framesync generally every...

Page 798: ...S_CONF register I2S_ conf register is used by the I2S module It informs about the I2S frame topology Table 719 SPI_I2C_usage register Offset 0x44 Bits Name Comments 31 08 Reserved when Ux 0 the switch...

Page 799: ...mit memory if necessary According to the data size the not used bits are filled with zero DTo1 DTo0 Transfer Output Data 00 8 32 8 bits 01 16 32 16 bits 10 24 32 24 bits 11 32 32 32 bits 23 invint inv...

Page 800: ...dentical to the transmit ones 04 LBsoi Switch output to input when Soi 0 no loopback is implemented when Soi 1 the output shift register is looped back inside the input register instead of the DIN pin...

Page 801: ...ize ST_Mode 1 data is stored read according its size in the I2S memory 23 MMdel informs if the external LRCK generated in master mode must be delayed by one bit MMdel 0 LRCK is not delayed Philips tim...

Page 802: ...the bank switching set by the I2S_CONF register interrupt is masked The interrupt is generated after those banks are switched nIT_BK 0 bank switching generates an interrupt nIT_BK 1 bank switching is...

Page 803: ...o the divider counter value When if will match the generated signal will toggle The output of the divider stage is then the input frequency divided by 2 D 15 0 1 02 Bypass To bypass divider for clock...

Page 804: ...Interrupt mask register Offset 0x54 Bits Name Comments 31 16 Reserved 15 14 Reserved Always write 1 mandatory 13 09 Reserved Always write 0 mandatory 08 IT_GPIO Mask for interrupt from GPIO pins 07 I...

Page 805: ...my Access Address byte ITp 0x5006_0000 ITch 0x5006_0001 ITi2S 0x5006_0002 ITtdm 0x5006_0003 Table 726 Interrupt status register Offset 0x58 Bits Name Comments 31 Reserved 30 IT Interrupt sent to the i...

Page 806: ...emory is described as RESET all 0 11 09 Reserved Interrupt requests from IPs after filtering through interrupt mask register 08 IT_GPIO 07 IT_KB 06 Reserved 05 Reserved 04 Reserved 03 ITtdm 02 ITi2s 0...

Page 807: ...buffered channels For narrow band 8 bit these bits are not relevant For wideband 16 bits the value can be 0 1 2 or 3 Off0 and Off1 are used In other cases the value can be 0 or 1 Only off0 is used 21...

Page 808: ...to inform that the last timeslot is switched on timeslot 0 As there is no time to store it in the memory and read back the sample will go directly from the shift in register to the shift out register...

Page 809: ...Clr Set Set Set Set Set Set Int_ITp Dummy read byte 50060000 Dummy read byte 50060001 Dummy read byte 50060002 Dummy read byte 50060003 Dummy read byte 50060004 Dummy read byte 50060005 Dummy read by...

Page 810: ...r block diagram 35 2 1 General purpose input output interface When GPIO mode is selected it is possible to program through APB Bus each of the 18 signals available as output or not they are always inp...

Page 811: ...ate Each time the timer expires the keyboard is scanned If only one key down is detected and it is the same key as on the previous scan a bit is set in the Status register indicating New Key Data The...

Page 812: ...00 RW 16 Mode Control Register GPIODIRREG 0x04 WO 18 Direction Register for GPIO outputs GPIODATAREG 0x08 RW 18 Data Register for GPIO input outputs STATUSREG 0x0C RW 2 Status Register KBREG 0x10 RO 8...

Page 813: ...egister only bit 1 is meaningful it is set to 1 by logic every time new data is available from keyboard This bit should be written to 0 once the data has been read from KBREG For interrupt handling th...

Page 814: ...alue Type Description Table 734 KBREG register bit assignments Bit Name Reset value Type Description 31 08 Not used 07 00 KBPRDATA 8 hFF RO Key code value Table 735 Key code table hex values COL 0 COL...

Page 815: ...s are available instead of only 6 as in the fixed part GPIO block described in Chapter 17 Hence width of GPIO Data Direction Register Interrupt Control Registers and Mode Control Register is 8bit 7 0...

Page 816: ...AM is driven by PLL1 this mode is called synchronous DRAM It is possible to use PLL2 to drive DRAM this mode is called asynchronous DRAM In asynchronous DRAM mode it is possible to change system frequ...

Page 817: ...MAIN Oscillator The following sections describe operative System Control State note that only operating states are described here for all intermediate states referred to Chapter 14 BS_System controll...

Page 818: ..._ENB usbdev_clkenb and AHB since the resume interrupt is registered by HCLK RTC All clocks to internal modules can be switched off except for RTC GPIO All clocks to internal modules can be switched of...

Page 819: ...ly in the NORMAL state in this case the hardware will execute transitioning as several steps Less than five clock cycles are required to change from one state to the other 37 2 3 SLOW In SLOW state MA...

Page 820: ...to wait PLL stabilization software and hardware look at section Section 37 2 3 SLOW for details 37 4 Dynamic clock switching Like DFS Dynamic Clock Switching DCS is a power management technique aimed...

Page 821: ...ivate only modules requested by the application This technique is to apply when a constant consumption is requested by the system It is useful when USB ports are not requested switch of USB PLL PLL3 a...

Page 822: ...o 3 3 33 3 33 3 3M M MH H Hz z z Multi layer AHB interconnect matrix High Speed subsystem Ethernet Mac USB 2 0 device Giga Ethernet JTAG ETM9 USB2 0 host 3 4 1 2 12 4 5 23 7 34 8 5 F L Reconfigurable...

Page 823: ...power off USB PLL PLL3 setting register USB2_PHY_CFG PLL pwdn to 1 Figure 111 Typical power consumption with DDR2 166 MHz and mobile DDR Note Typical current and power values listed in this chapter ar...

Page 824: ...ow current consumption on different input voltages Note 3 3V current is primarily dependent on the capacitive loading frequency and utilization of the external buses Table 740 Power and current consum...

Page 825: ...n bold delta values in normal 37 8 2 IPs power All IPs are connected to Vcore 1 2Volt to power the I F logic with the internal buses some IPs are also connected to other voltages The following table d...

Page 826: ...oftware and requires to have a second level boot software Xloader in NOR NAND Flash Last three types USB UART Ethernet are meant to boot without Flash memories USB boot is used to upgrade 1st to 3rd l...

Page 827: ...f Non flash booting it receives second level boot code execute it and then receives third level boot code and jumps into it 3 Upgrade the flash through USB BootROM This is the second level boot code I...

Page 828: ...s where X Loader is copied in the shadow memory is specified in the X Loader s header 38 3 3 System controller The system controller is used to program control the system clock mode and frequency Afte...

Page 829: ...s section contains all the routines required to boot on SPEAr300 38 4 4 X Loader and U boot Header typedef struct image_header uint32_t ih_magic Image Header Magic Number uint32_t ih_hcrc Image Header...

Page 830: ...ceived header with 0x2705_1956 3 Checking the CRC of the image header and image received with the CRCs present in the header 38 5 Boot flows An overview diagrammatical representation of boot flow is g...

Page 831: ...tROM tries to authenticate X Loader if X loader is found then BootROM copies X Loader from Flash to shadow memory area and jumps to X Loader in shadow memory The load address of X Loader is also speci...

Page 832: ...e 1st word of spare area of every block It should be 0xFF If bad then skip to next block Read the whole page in a buffer buffer size equals page size search for X Loader If found return start address...

Page 833: ...NAND starting from first block 2 Before reading block its sanity is checked by reading 1 st word of spare area on first page It should be 0xFF 0xFF represents sanity X Loader Found YES No USB boot Co...

Page 834: ...specified in the command once all the data is received BootROM changes the USB state machine to EXEC phase and decodes the type of data if the received data is DDR Driver then BootROM jumps to loadad...

Page 835: ...iptorType Byte 0x01 2 bcdUSB Word 0x200 4 bDeviceClass Byte 0x00 5 bDeviceSubClass Byte 0x00 6 bDeviceProtocol Byte 0x00 7 wMaxPacketSize0 Byte 0x40 8 idVendor Word 0x0483 10 iProduct Word 0x3801 12 b...

Page 836: ...bAlternateSetting Byte 0x00 4 bNumEndpoints Byte 0x02 5 bInterfaceClass Byte 0x00 6 interfaceSubClass Byte 0x00 7 bInterfaceProtocol Byte 0x02 8 iInterface Byte 0x01 Table 748 Bulk OUT endpoint Offset...

Page 837: ...RM0082 BootROM Doc ID 018672 Rev 1 837 844 5 String descriptors Table 750 String descriptors Offset Field Size Value 0 bLength Byte 0x04 1 bDescriptorType Byte 0x03 2 bEndpointAddress Byte 0x0409...

Page 838: ...ommand Change state machine GET_DATA Wait for expected number of bytes from Host Receive DDR driver and change state to Exec Execute DDR driver and jump back to BootROM Change state machine GET_CMD Wa...

Page 839: ...baud rate of 11250 bits per second bps It then runs the X Loader image which initializes the PLLs and DDR and then returns back the control to Boot code After this X modem protocol is again used to d...

Page 840: ...118 Serial boot Initialize UART Receive X Loader through X modem protocol Authenticate X Loader Run X Loader from eSRAM area Passed Return to BootROM Receive U boot through X modem protocol Authentica...

Page 841: ...obtaining the IP from a server This is essentially the first phase of booting in the case of Ethernet boot The second stage of booting starts after the device has its own IP and the device can communi...

Page 842: ...e Ethernet IP Received Receive X Loader through TFTP Authenticate X Loader Passed Run X Loader and return to BootROM Notes 1 TFTP timeout is 5 seconds Notes 1 DHCP timeout is 5 seconds Receive U boot...

Page 843: ...RM0082 Document revision history Doc ID 018672 Rev 1 843 844 39 Document revision history Table 751 Document revision history Date Revision Changes 29 Apr 2011 1 Initial Release...

Page 844: ...INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SA...

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