HS_USB2.0 host
RM0082
416/844
Doc ID 018672 Rev 1
22.5.3
List processor block
The list processor block acts as a main controller of the entire controller. It has multiple state
machines to implement List Service Flow, List Priority, USB-States, ED, TD Service,
StatusWriteBack, TD Retirement, and so on as per the OHCI specification. Additionally, this
block implements a controller which interfaces with HCI_master and hsie, helping them in
the data transfer from system memory to USB and USB to system memory.
The following submodules are included:
●
USB states
●
List service flow
●
ED-TD block
●
HCI master interface logic
●
Data read write logic
22.5.4
RootHub and HSIE blocks
Since implementation varies, most of the functionality of the RootHub is implemented in the
Port Configuration Block. This logic is common to any user configuration. The logic in this
block acts as a wrapper around HSIE and interface with Host Controller’s List Processor,
FIFO and OHCI registers. This block also implements the control logic to synchronize the
interface between HSIE and port S/M.
This block implements the following submodules:
●
Reset_Resume
●
DPLL
●
HSIE
22.5.5
Digital PLL block (DPLL)
The function of the DPLL Block is to extract the clock and data information from the USB
Data received from the different transceiver. The Digital PLL runs on a 48 MHz user-
provided clock to extract the clock information from the USB for both Full-Speed and Low-
speed data. The two signals D+ and D- of the USB lines are passed through a differential
receiver (external to the UHOSTC controller) and a NRZI formatted data is obtained from
the output of the differential receivers. The output of the differential receiver is then used by
the Digital PLL to extract clock information. The PLL Block also has a SE0 Detect Logic to
detect the Single Ended Zero (SE0) in the data stream. The circuit in this module extracts
clock from either high-speed data or low-speed data indicated by SIE_Switch HCLK input
from SIETx State Machine.
22.5.6 HSIE
functionality
The functionality of the Host Serial Interface Engine (HSIE) is to receive and transmit the
USB data over D+ and D- lines in accordance with the USB protocol. During the reception of
USB data, the D+ and D- signals are passed through the differential receiver (which is
external to the UHOSTC controller) to get a single ended bit stream that is passed through
the PLL Block to extract the clock and data information. The Clock and data are passed to
the SIE Block to identify the Sync Pattern and for NRZI-NRZ conversion. This NRZ data is
then passed through the Bit Stripper which strips off the excessive zeros inserted, The data
stream is initially passed through the PID Decode and checker to identify different PIDs.
Depending upon the type of PID, the HSIE block handles the protocol accordingly.
